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Searched refs:DMA_TCD_CSR_DREQ_MASK (Results 1 – 25 of 97) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/
Dfsl_ad_edma.h534 (base->CH[channel].TCD_CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_AD_EnableAutoStopRequest()
698 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_AD_TcdEnableAutoStopRequest()
Dfsl_edma.h535 (base->CH[channel].TCD_CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_EnableAutoStopRequest()
699 tcd->CSR = (tcd->CSR & (~(uint16_t)DMA_TCD_CSR_DREQ_MASK)) | DMA_TCD_CSR_DREQ(enable); in EDMA_TcdEnableAutoStopRequest()
Dfsl_ad_edma.c542 tcd->CSR = (tcd->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_AD_TcdSetTransferConfig()
1102 handle->base->CH[handle->channel].TCD_CSR |= DMA_TCD_CSR_DREQ_MASK; in EDMA_AD_SubmitTransfer()
1159 …dle->tcdPool[previousTcd].CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_AD_SubmitTransfer()
1178 … csr = (tcdRegs->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_AD_SubmitTransfer()
Dfsl_edma.c570 tcd->CSR = (tcd->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_TcdSetTransferConfig()
1134 handle->base->CH[handle->channel].TCD_CSR |= DMA_TCD_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
1191 …dle->tcdPool[previousTcd].CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
1210 … csr = (tcdRegs->CSR | (uint16_t)DMA_TCD_CSR_ESG_MASK) & ~(uint16_t)DMA_TCD_CSR_DREQ_MASK; in EDMA_SubmitTransfer()
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K118_DMA.h758 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
761 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K116_DMA.h758 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
761 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K148_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K144W_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K144_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K142W_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K142_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
DS32K146_DMA.h1118 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
1121 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2832 #define DMA_TCD_CSR_DREQ_MASK DMA_TCD_TCD0_CSR_DREQ_MASK macro
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h2395 #define DMA_TCD_CSR_DREQ_MASK EDMA3_TCD_CSR_DREQ_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h4625 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
4631 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h4625 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
4631 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h4625 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
4631 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h4625 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
4631 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h6836 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
6842 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h7604 #define DMA_TCD_CSR_DREQ_MASK (0x8U) macro
7610 … (((uint16_t)(((uint16_t)(x)) << DMA_TCD_CSR_DREQ_SHIFT)) & DMA_TCD_CSR_DREQ_MASK)

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