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Searched refs:DMA_CSR_INTHALF_MASK (Results 1 – 25 of 77) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/
Dfsl_edma_core.h21 #define DMA_CSR_INTHALF_MASK (0x4U) macro
134 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK)
138 …EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
Dfsl_edma.c860 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterruptsExt()
885 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterruptsExt()
1237 EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
1264 EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterrupts()
Dfsl_edma.h158 …kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to hal…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/
Dfsl_edma_core.h21 #define DMA_CSR_INTHALF_MASK (0x4U) macro
134 (EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK)
138 …EDMA_TCD_CSR(EDMA_TCD_BASE(base, channel), EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK)
Dfsl_edma.c860 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterruptsExt()
885 EDMA_TCD_CSR(tcd, EDMA_TCD_TYPE(base)) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterruptsExt()
1237 EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
1264 EDMA_TCD_CSR(tcd, kEDMA_EDMA4Flag) &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterrupts()
Dfsl_edma.h158 …kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to hal…
/hal_nxp-latest/mcux/mcux-sdk/drivers/edma/
Dfsl_edma.c402 base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK; in EDMA_EnableChannelInterrupts()
433 base->TCD[channel].CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_DisableChannelInterrupts()
682 tcd->CSR |= DMA_CSR_INTHALF_MASK; in EDMA_TcdEnableInterrupts()
706 tcd->CSR &= ~(uint16_t)DMA_CSR_INTHALF_MASK; in EDMA_TcdDisableInterrupts()
Dfsl_edma.h129 …kEDMA_HalfInterruptEnable = DMA_CSR_INTHALF_MASK, /*!< Enable interrupt while major count to hal…
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h2403 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2409 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h2407 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2413 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h2311 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2317 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h2427 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2433 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h2565 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2571 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h2994 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3000 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h2921 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2927 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h2996 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3002 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h2995 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3001 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h3352 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3358 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h3190 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3196 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h3194 #define DMA_CSR_INTHALF_MASK (0x4U) macro
3200 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h2429 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2435 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h2749 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2755 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h2923 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2929 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h2750 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2756 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h2922 #define DMA_CSR_INTHALF_MASK (0x4U) macro
2928 … (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)

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