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Searched refs:DMA_COMMON_INTENSET1_INTEN32_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h6025 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
6031 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
DMIMXRT685S_cm33.h11865 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
11871 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h11865 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
11871 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h9451 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
9457 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
DMIMXRT595S_cm33.h15837 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
15843 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h8936 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
8942 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h8936 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
8942 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h15833 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
15839 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h15836 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
15842 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h8935 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
8941 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h25586 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
25592 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h25586 #define DMA_COMMON_INTENSET1_INTEN32_MASK (0x1U) macro
25592 …t32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET1_INTEN32_SHIFT)) & DMA_COMMON_INTENSET1_INTEN32_MASK)