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Searched refs:DMA_COMMON_ENABLESET_ENABLE0_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h7638 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
7644 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
DMIMXRT595S_cm33.h14024 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
14030 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h6523 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
6529 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h6523 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
6529 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h14020 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
14026 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h14023 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
14029 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h6522 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
6528 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h23933 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
23939 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h23933 #define DMA_COMMON_ENABLESET_ENABLE0_MASK (0x1U) macro
23939 …t32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENABLE0_SHIFT)) & DMA_COMMON_ENABLESET_ENABLE0_MASK)