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Searched refs:DMA_COMMON_ENABLECLR_CLR0_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h7948 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
7954 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
DMIMXRT595S_cm33.h14334 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
14340 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h6953 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
6959 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h6953 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
6959 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h14330 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
14336 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h14333 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
14339 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h6952 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
6958 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h24211 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
24217 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h24211 #define DMA_COMMON_ENABLECLR_CLR0_MASK (0x1U) macro
24217 …(((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR0_SHIFT)) & DMA_COMMON_ENABLECLR_CLR0_MASK)