Home
last modified time | relevance | path

Searched refs:DMA_COMMON_ENABLECLR1_CLR32_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h8211 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
8217 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
DMIMXRT595S_cm33.h14597 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
14603 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h7216 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
7222 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h7216 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
7222 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h14593 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
14599 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h14596 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
14602 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36.h7215 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
7221 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h24474 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
24480 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h24474 #define DMA_COMMON_ENABLECLR1_CLR32_MASK (0x1U) macro
24480 …int32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR1_CLR32_SHIFT)) & DMA_COMMON_ENABLECLR1_CLR32_MASK)