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Searched refs:DMA_CH_CSR_ERQ_MASK (Results 1 – 25 of 93) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/dma3/
Dfsl_ad_edma.c1245 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_AD_SubmitTransfer()
1268 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_AD_StartTransfer()
1283 …if ((handle->base->CH[handle->channel].CH_CSR & DMA_CH_CSR_ERQ_MASK & (1U << handle->channel)) == … in EDMA_AD_StartTransfer()
1296 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_AD_StartTransfer()
1319 (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_ERQ_MASK; in EDMA_AD_StopTransfer()
1333 (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_ERQ_MASK; in EDMA_AD_AbortTransfer()
Dfsl_edma.c1286 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_SubmitTransfer()
1309 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
1324 …if ((handle->base->CH[handle->channel].CH_CSR & DMA_CH_CSR_ERQ_MASK & (1U << handle->channel)) == … in EDMA_StartTransfer()
1342 … (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) | DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
1365 (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_ERQ_MASK; in EDMA_StopTransfer()
1379 (handle->base->CH[handle->channel].CH_CSR & (~DMA_CH_CSR_DONE_MASK)) & ~DMA_CH_CSR_ERQ_MASK; in EDMA_AbortTransfer()
Dfsl_ad_edma.h737 base->CH[channel].CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_AD_EnableChannelRequest()
752 base->CH[channel].CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_AD_DisableChannelRequest()
Dfsl_edma.h738 base->CH[channel].CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
753 base->CH[channel].CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
/hal_nxp-latest/mcux/mcux-sdk/drivers/edma4/
Dfsl_edma.h1459 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
1478 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
Dfsl_edma.c2406 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2411 if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) in EDMA_StartTransfer()
2421 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2442 …hannelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); in EDMA_StopTransfer()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/drivers/edma4/
Dfsl_edma.h1459 EDMA_CHANNEL_BASE(base, channel)->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_EnableChannelRequest()
1478 EDMA_CHANNEL_BASE(base, channel)->CH_CSR &= ~DMA_CH_CSR_ERQ_MASK; in EDMA_DisableChannelRequest()
Dfsl_edma.c2413 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2418 if ((handle->channelBase->CH_CSR & DMA_CH_CSR_ERQ_MASK) == 0U) in EDMA_StartTransfer()
2428 handle->channelBase->CH_CSR |= DMA_CH_CSR_ERQ_MASK; in EDMA_StartTransfer()
2449 …hannelBase->CH_CSR = handle->channelBase->CH_CSR & (~(DMA_CH_CSR_DONE_MASK | DMA_CH_CSR_ERQ_MASK)); in EDMA_StopTransfer()
/hal_nxp-latest/s32/mcux/devices/S32K344/
DS32K344_device.h2576 #define DMA_CH_CSR_ERQ_MASK DMA_TCD_CH0_CSR_ERQ_MASK macro
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_device.h2091 #define DMA_CH_CSR_ERQ_MASK EDMA3_TCD_CH_CSR_ERQ_MASK macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA142/
DMCXA142.h4173 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
4179 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA143/
DMCXA143.h4173 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
4179 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA153/
DMCXA153.h4173 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
4179 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA152/
DMCXA152.h4173 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
4179 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA146/
DMCXA146.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA145/
DMCXA145.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA144/
DMCXA144.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA156/
DMCXA156.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA154/
DMCXA154.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXA155/
DMCXA155.h6384 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
6390 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/
DMCXW716A.h7139 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
7145 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h17922 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
17928 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
DMIMXRT735S_cm33_core1.h17960 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
17966 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/
DMCXW716C.h9308 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
9314 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h17960 #define DMA_CH_CSR_ERQ_MASK (0x1U) macro
17966 … (((uint32_t)(((uint32_t)(x)) << DMA_CH_CSR_ERQ_SHIFT)) & DMA_CH_CSR_ERQ_MASK)

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