Searched refs:DMAR0 (Results 1 – 10 of 10) sorted by relevance
| /hal_nxp-latest/s32/drivers/s32ze/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32XX.h | 141 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
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| D | Adc_Sar_Ip_HeaderWrapper_S32XX_AE.h | 136 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32K3.h | 171 #define DMAR(base, regIndex) REG_ACCESS((base)->DMAR0, (regIndex))
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_ADC.h | 92 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_ADC.h | 97 …__IO uint32_t DMAR0; /**< DMA Request Enable For Precision Inputs, off… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/ |
| D | MIMX9131.h | 629 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/ |
| D | MIMX9352_cm33.h | 62823 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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| D | MIMX9352_ca55.h | 631 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9596/ |
| D | MIMX9596_ca55.h | 565 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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| D | MIMX9596_cm7.h | 555 __IO uint32_t DMAR0; /**< DMA 0, offset: 0x44 */ member
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