Searched refs:DMA (Results 1 – 25 of 137) sorted by relevance
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243 base->DMA[channel].SAR = srcAddr; in DMA_SetSourceAddress()257 base->DMA[channel].DAR = destAddr; in DMA_SetDestinationAddress()271 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(size); in DMA_SetTransferSize()302 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_CS_MASK)) | DMA_DCR_CS(enable); in DMA_EnableCycleSteal()319 base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_AA_MASK)) | DMA_DCR_AA(enable); in DMA_EnableAutoAlign()336 …base->DMA[channel].DCR = (base->DMA[channel].DCR & (~DMA_DCR_EADREQ_MASK)) | DMA_DCR_EADREQ(enable… in DMA_EnableAsyncRequest()349 base->DMA[channel].DCR |= DMA_DCR_EINT(true); in DMA_EnableInterrupts()362 base->DMA[channel].DCR &= ~DMA_DCR_EINT_MASK; in DMA_DisableInterrupts()381 base->DMA[channel].DCR |= DMA_DCR_ERQ_MASK; in DMA_EnableChannelRequest()394 base->DMA[channel].DCR &= ~DMA_DCR_ERQ_MASK; in DMA_DisableChannelRequest()[all …]
112 base->DMA[channel].DSR_BCR |= DMA_DSR_BCR_DONE(true); in DMA_ResetChannel()114 base->DMA[channel].SAR = 0; in DMA_ResetChannel()115 base->DMA[channel].DAR = 0; in DMA_ResetChannel()116 base->DMA[channel].DSR_BCR = 0; in DMA_ResetChannel()118 base->DMA[channel].DCR = DMA_DCR_D_REQ(true) | DMA_DCR_CS(true); in DMA_ResetChannel()153 base->DMA[channel].SAR = config->srcAddr; in DMA_SetTransferConfig()155 base->DMA[channel].DAR = config->destAddr; in DMA_SetTransferConfig()157 base->DMA[channel].DSR_BCR = DMA_DSR_BCR_BCR(config->transferSize); in DMA_SetTransferConfig()159 tmpreg = base->DMA[channel].DCR; in DMA_SetTransferConfig()163 base->DMA[channel].DCR = tmpreg; in DMA_SetTransferConfig()[all …]
12 bool "DMA Driver"16 DMA Driver
1 #Description: DMA Driver; user_visible: True
337 base->CHANNEL[channel].DMA &= ~(uint16_t)TMR_DMA_IEFDE_MASK; in QTMR_EnableInterrupts()611 reg = base->CHANNEL[channel].DMA; in QTMR_EnableDma()629 base->CHANNEL[channel].DMA = reg; in QTMR_EnableDma()644 reg = base->CHANNEL[channel].DMA; in QTMR_DisableDma()660 base->CHANNEL[channel].DMA = reg; in QTMR_DisableDma()
12 bool "DMA Driver"15 DMA Driver
34 bool "FLEXSPI DMA Driver"37 FLEXSPI DMA Driver
1 #Description: FLEXSPI DMA Driver; user_visible: True
35 bool "DMIC DMA Driver"38 DMIC DMA Driver
1 #Description: DMIC DMA Driver; user_visible: True
12 bool "FLEXIO I2S DMA Driver"15 FLEXIO I2S DMA Driver
34 bool "FLEXIO SPI DMA Driver"37 FLEXIO SPI DMA Driver
23 bool "FLEXIO UART DMA Driver"26 FLEXIO UART DMA Driver
174 #define DMA ((DMA_Type*)DMA_BASE) macro175 #define DMA_BASE_PTRS {DMA}
58 # # description: FLEXIO I2S DMA Driver61 # # description: FLEXIO SPI DMA Driver64 # # description: FLEXIO UART DMA Driver73 # # description: SAI DMA Driver250 # # description: DMA Driver
61 #error This SOC does not have DMA available!73 #error This SOC does not have DMA or EDMA available!
58 # # description: FLEXIO I2S DMA Driver61 # # description: FLEXIO SPI DMA Driver64 # # description: FLEXIO UART DMA Driver238 # # description: DMA Driver
52 # # description: FLEXIO I2S DMA Driver55 # # description: FLEXIO SPI DMA Driver58 # # description: FLEXIO UART DMA Driver232 # # description: DMA Driver
1 #Description: LCDIC DMA Driver; user_visible: True
1 #Description: I2C DMA Driver; user_visible: True
1 #Description: UART DMA Driver; user_visible: True
1 #Description: SPI DMA Driver; user_visible: True
1 #Description: SPIFI DMA Driver; user_visible: True
1 #Description: LPUART DMA Driver; user_visible: True
1 #Description: FLEXCOMM SPI DMA Driver; user_visible: True
