Home
last modified time | relevance | path

Searched refs:DEV_ASSERT_QSPI (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k3/Fls/src/
DQspi_Ip.c218 DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount); in Qspi_Ip_InitLutSeq()
224 DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount); in Qspi_Ip_InitLutSeq()
229 DEV_ASSERT_QSPI(lutIdx < FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_InitLutSeq()
975 DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT); in Qspi_Ip_RunCommand()
976 DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID); in Qspi_Ip_RunCommand()
977 DEV_ASSERT_QSPI(addr < state->configuration->memSize); in Qspi_Ip_RunCommand()
1011 DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT); in Qspi_Ip_RunReadCommand()
1012 DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID); in Qspi_Ip_RunReadCommand()
1013 DEV_ASSERT_QSPI(addr < state->configuration->memSize); in Qspi_Ip_RunReadCommand()
1014 DEV_ASSERT_QSPI((size > 0UL) && ((addr + size) <= state->configuration->memSize)); in Qspi_Ip_RunReadCommand()
[all …]
DQspi_Ip_Controller.c1050 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_AhbSetup()
1051 DEV_ASSERT_QSPI(0U == (config->sizes[0U] & 7U)); in Qspi_Ip_AhbSetup()
1052 DEV_ASSERT_QSPI(((uint32)config->sizes[0U] + in Qspi_Ip_AhbSetup()
1205 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetLut()
1206 DEV_ASSERT_QSPI(LutRegister < QuadSPI_LUT_COUNT); in Qspi_Ip_SetLut()
1224 DEV_ASSERT_QSPI(Instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1225 DEV_ASSERT_QSPI(StartLutRegister < QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1226 DEV_ASSERT_QSPI(Size <= FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_WriteLuts_Privileged()
1227 DEV_ASSERT_QSPI((StartLutRegister + Size) <= QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1251 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetAhbSeqId_Privileged()
[all …]
DQspi_Ip_Sfdp.c3974 DEV_ASSERT_QSPI(pConnect != NULL_PTR); in Qspi_Ip_ReadSfdp()
3975 DEV_ASSERT_QSPI(pConfig != NULL_PTR); in Qspi_Ip_ReadSfdp()
3976 …DEV_ASSERT_QSPI((pConfig->lutSequences.lutOps != NULL_PTR) && (pConfig->lutSequences.opCount > 0U)… in Qspi_Ip_ReadSfdp()
/hal_nxp-latest/s32/drivers/s32ze/Mem_EXFLS/src/
DQspi_Ip.c231 DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount); in Qspi_Ip_InitLutSeq()
239 DEV_ASSERT_QSPI(vLutIdx < state->configuration->lutSequences.opCount); in Qspi_Ip_InitLutSeq()
246 DEV_ASSERT_QSPI(pLutIdx < FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_InitLutSeq()
1024 DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT); in Qspi_Ip_RunCommand()
1025 DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID); in Qspi_Ip_RunCommand()
1026 DEV_ASSERT_QSPI(addr < state->configuration->memSize); in Qspi_Ip_RunCommand()
1062 DEV_ASSERT_QSPI(instance < QSPI_IP_MEM_INSTANCE_COUNT); in Qspi_Ip_RunReadCommand()
1063 DEV_ASSERT_QSPI(lut != QSPI_IP_LUT_INVALID); in Qspi_Ip_RunReadCommand()
1064 DEV_ASSERT_QSPI(addr < state->configuration->memSize); in Qspi_Ip_RunReadCommand()
1065 DEV_ASSERT_QSPI((size > 0UL) && ((addr + size) <= state->configuration->memSize)); in Qspi_Ip_RunReadCommand()
[all …]
DQspi_Ip_Controller.c1283 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_AhbSetup()
1284 DEV_ASSERT_QSPI(0U == (config->sizes[0U] & 7U)); in Qspi_Ip_AhbSetup()
1285 DEV_ASSERT_QSPI(((uint32)config->sizes[0U] + in Qspi_Ip_AhbSetup()
1438 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetLut()
1439 DEV_ASSERT_QSPI(LutRegister < QuadSPI_LUT_COUNT); in Qspi_Ip_SetLut()
1460 DEV_ASSERT_QSPI(Instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1461 DEV_ASSERT_QSPI(StartLutRegister < QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1462 DEV_ASSERT_QSPI(Size <= FEATURE_QSPI_LUT_SEQUENCE_SIZE); in Qspi_Ip_WriteLuts_Privileged()
1463 DEV_ASSERT_QSPI((StartLutRegister + Size) <= QuadSPI_LUT_COUNT); in Qspi_Ip_WriteLuts_Privileged()
1489 DEV_ASSERT_QSPI(instance < QuadSPI_INSTANCE_COUNT); in Qspi_Ip_SetAhbSeqId_Privileged()
[all …]
DQspi_Ip_Sfdp.c4029 DEV_ASSERT_QSPI(pConnect != NULL_PTR); in Qspi_Ip_ReadSfdp()
4030 DEV_ASSERT_QSPI(pConfig != NULL_PTR); in Qspi_Ip_ReadSfdp()
4031 …DEV_ASSERT_QSPI((pConfig->lutSequences.lutOps != NULL_PTR) && (pConfig->lutSequences.opCount > 0U)… in Qspi_Ip_ReadSfdp()
/hal_nxp-latest/s32/soc/s32k344/include/
DQspi_Ip_Cfg.h75 #define DEV_ASSERT_QSPI(x) macro