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Searched refs:DDRPHY_VTCR1_RESERVED_27_MASK (Results 1 – 15 of 15) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h18403 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18407 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h18403 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18407 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX3/
DMIMX8DX3_cm4.h18403 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18407 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX6/
DMIMX8QX6_dsp.h18997 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
19000 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
DMIMX8QX6_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX6/
DMIMX8DX6_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX5/
DMIMX8QX5_cm4.h18404 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18408 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX5/
DMIMX8DX5_cm4.h18405 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18409 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX6/
DMIMX8UX6_cm4.h18406 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18410 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UX5/
DMIMX8UX5_cm4.h18406 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18410 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX4/
DMIMX8QX4_cm4.h18402 #define DDRPHY_VTCR1_RESERVED_27_MASK (0x8000000U) macro
18406 … (((uint32_t)(((uint32_t)(x)) << DDRPHY_VTCR1_RESERVED_27_SHIFT)) & DDRPHY_VTCR1_RESERVED_27_MASK)