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Searched refs:DDRC_TIMING_CFG_0_WRT_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_DDRC.h734 #define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) macro
737 … (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9131/
DMIMX9131.h13167 #define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) macro
13170 … (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX9352/
DMIMX9352_cm33.h11434 #define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) macro
11437 … (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK)
DMIMX9352_ca55.h14339 #define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) macro
14342 … (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK)