1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DDRC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DDRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DDRC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DDRC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DDRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DDRC_Peripheral_Access_Layer DDRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DDRC - Size of Registers Arrays */ 72 #define DDRC_CS_BNDS_COUNT 2u 73 #define DDRC_CS_CONFIG_COUNT 2u 74 #define DDRC_DDR_MTP_COUNT 10u 75 76 /** DDRC - Register Layout Typedef */ 77 typedef struct { 78 struct DDRC_CS_BNDS { /* offset: 0x0, array step: 0x8 */ 79 __IO uint32_t CS_BNDS; /**< Rank 0 Memory Bounds..Rank 1 Memory Bounds, array offset: 0x0, array step: 0x8 */ 80 uint8_t RESERVED_0[4]; 81 } CS_BNDS[DDRC_CS_BNDS_COUNT]; 82 uint8_t RESERVED_0[16]; 83 __IO uint32_t REMAP_0A; /**< Remap Region 0A Configuration, offset: 0x20 */ 84 __IO uint32_t REMAP_0B; /**< Remap Region 0B Configuration, offset: 0x24 */ 85 __IO uint32_t REMAP_1A; /**< Remap Region 1A Configuration, offset: 0x28 */ 86 __IO uint32_t REMAP_1B; /**< Remap Region 1B Configuration, offset: 0x2C */ 87 __IO uint32_t REMAP_2A; /**< Remap Region 2A Configuration, offset: 0x30 */ 88 __IO uint32_t REMAP_2B; /**< Remap Region 2B Configuration, offset: 0x34 */ 89 __IO uint32_t REMAP_3A; /**< Remap Region 3A Configuration, offset: 0x38 */ 90 __IO uint32_t REMAP_3B; /**< Remap Region 3B Configuration, offset: 0x3C */ 91 __IO uint32_t DDR_ADDR_DEC_0; /**< DDRC Address Decode 0, offset: 0x40 */ 92 __IO uint32_t DDR_ADDR_DEC_1; /**< DDRC Address Decode 1, offset: 0x44 */ 93 __IO uint32_t DDR_ADDR_DEC_2; /**< DDRC Address Decode 2, offset: 0x48 */ 94 __IO uint32_t DDR_ADDR_DEC_3; /**< DDRC Address Decode 3, offset: 0x4C */ 95 __IO uint32_t DDR_ADDR_DEC_4; /**< DDRC Address Decode 4, offset: 0x50 */ 96 __IO uint32_t DDR_ADDR_DEC_5; /**< DDRC Address Decode 5, offset: 0x54 */ 97 __IO uint32_t DDR_ADDR_DEC_6; /**< DDRC Address Decode 6, offset: 0x58 */ 98 __IO uint32_t DDR_ADDR_DEC_7; /**< DDRC Address Decode 7, offset: 0x5C */ 99 __IO uint32_t DDR_ADDR_DEC_8; /**< DDRC Address Decode 8, offset: 0x60 */ 100 __IO uint32_t DDR_ADDR_DEC_9; /**< DDRC Address Decode 9, offset: 0x64 */ 101 uint8_t RESERVED_1[24]; 102 __IO uint32_t CS_CONFIG[DDRC_CS_CONFIG_COUNT]; /**< Rank 0 Configuration..Rank 1 Configuration, array offset: 0x80, array step: 0x4 */ 103 uint8_t RESERVED_2[120]; 104 __IO uint32_t TIMING_CFG_3; /**< DDR SDRAM Timing Configuration 3, offset: 0x100 */ 105 __IO uint32_t TIMING_CFG_0; /**< DDR SDRAM Timing Configuration 0, offset: 0x104 */ 106 __IO uint32_t TIMING_CFG_1; /**< DDR SDRAM Timing Configuration 1, offset: 0x108 */ 107 __IO uint32_t TIMING_CFG_2; /**< DDR SDRAM Timing Configuration 2, offset: 0x10C */ 108 __IO uint32_t DDR_SDRAM_CFG; /**< DDR SDRAM Control Configuration, offset: 0x110 */ 109 __IO uint32_t DDR_SDRAM_CFG_2; /**< DDR SDRAM Control Configuration 2, offset: 0x114 */ 110 uint8_t RESERVED_3[8]; 111 __IO uint32_t DDR_SDRAM_MD_CNTL; /**< DDR SDRAM Mode Control, offset: 0x120 */ 112 __IO uint32_t DDR_SDRAM_INTERVAL; /**< DDR SDRAM Interval Configuration, offset: 0x124 */ 113 __IO uint32_t DDR_DATA_INIT; /**< DDR SDRAM Data Initialization, offset: 0x128 */ 114 uint8_t RESERVED_4[52]; 115 __IO uint32_t TIMING_CFG_4; /**< DDR SDRAM Timing Configuration 4, offset: 0x160 */ 116 uint8_t RESERVED_5[8]; 117 __IO uint32_t TIMING_CFG_7; /**< DDR SDRAM Timing Configuration 7, offset: 0x16C */ 118 __IO uint32_t DDR_ZQ_CNTL; /**< DDR SDRAM ZQ Calibration Control, offset: 0x170 */ 119 uint8_t RESERVED_6[8]; 120 __IO uint32_t DDR_SR_CNTR; /**< DDR SDRAM Self-Refresh Counter, offset: 0x17C */ 121 uint8_t RESERVED_7[208]; 122 __IO uint32_t TIMING_CFG_8; /**< DDR SDRAM Timing Configuration 8, offset: 0x250 */ 123 __IO uint32_t TIMING_CFG_9; /**< DDR SDRAM timing configuration 9, offset: 0x254 */ 124 uint8_t RESERVED_8[4]; 125 __IO uint32_t TIMING_CFG_11; /**< DDR SDRAM Timing Configuration 11, offset: 0x25C */ 126 __IO uint32_t DDR_SDRAM_CFG_3; /**< DDR SDRAM Control Configuration 3, offset: 0x260 */ 127 uint8_t RESERVED_9[92]; 128 __I uint32_t DDR_SDRAM_REF_RATE; /**< DDR Refresh Rate, offset: 0x2C0 */ 129 uint8_t RESERVED_10[1340]; 130 __IO uint32_t TX_CFG_1; /**< Transaction Configuration Register 1, offset: 0x800 */ 131 uint8_t RESERVED_11[28]; 132 __IO uint32_t FFI_CFG; /**< Freedom From Interference Configuration, offset: 0x820 */ 133 __IO uint32_t FFI_CFG2; /**< Freedom From Interference Configuration 2, offset: 0x824 */ 134 uint8_t RESERVED_12[764]; 135 __IO uint32_t DDRDSR_2; /**< DDR SDRAM Debug Status 2, offset: 0xB24 */ 136 uint8_t RESERVED_13[208]; 137 __I uint32_t DDR_IP_REV1; /**< DDRC Revision 1, offset: 0xBF8 */ 138 uint8_t RESERVED_14[260]; 139 __IO uint32_t DDR_MTCR; /**< DDR SDRAM Memory Test Control, offset: 0xD00 */ 140 uint8_t RESERVED_15[28]; 141 __IO uint32_t DDR_MTP[DDRC_DDR_MTP_COUNT]; /**< DDR SDRAM Memory Test Pattern n, array offset: 0xD20, array step: 0x4 */ 142 uint8_t RESERVED_16[24]; 143 __IO uint32_t DDR_MT_ST_EXT_ADDR; /**< DDR SDRAM Memory Test Start Extended Address, offset: 0xD60 */ 144 __IO uint32_t DDR_MT_ST_ADDR; /**< DDR SDRAM Memory Test Start Address, offset: 0xD64 */ 145 __IO uint32_t DDR_MT_END_EXT_ADDR; /**< DDR SDRAM Memory Test End Extended Address, offset: 0xD68 */ 146 __IO uint32_t DDR_MT_END_ADDR; /**< DDR SDRAM Memory Test End Address, offset: 0xD6C */ 147 uint8_t RESERVED_17[144]; 148 __IO uint32_t PMGC0; /**< Performance Monitor Global Control, offset: 0xE00 */ 149 uint8_t RESERVED_18[12]; 150 __IO uint32_t PMLCA0; /**< Performance Monitor Local Control A0, offset: 0xE10 */ 151 __IO uint32_t PMLCB0; /**< Performance Monitor Local Control B0, offset: 0xE14 */ 152 __IO uint32_t PMC0A; /**< PMC 0a, offset: 0xE18 */ 153 __IO uint32_t PMC0B; /**< PMC 0b, offset: 0xE1C */ 154 __IO uint32_t PMLCA1; /**< Performance Monitor Local Control A, offset: 0xE20 */ 155 __IO uint32_t PMLCB1; /**< Performance Monitor Local Control B, offset: 0xE24 */ 156 __IO uint32_t PMC1; /**< Performance Monitor Counter, offset: 0xE28 */ 157 uint8_t RESERVED_19[4]; 158 __IO uint32_t PMLCA2; /**< Performance Monitor Local Control A, offset: 0xE30 */ 159 __IO uint32_t PMLCB2; /**< Performance Monitor Local Control B, offset: 0xE34 */ 160 __IO uint32_t PMC2; /**< Performance Monitor Counter, offset: 0xE38 */ 161 uint8_t RESERVED_20[4]; 162 __IO uint32_t PMLCA3; /**< Performance Monitor Local Control A, offset: 0xE40 */ 163 __IO uint32_t PMLCB3; /**< Performance Monitor Local Control B, offset: 0xE44 */ 164 __IO uint32_t PMC3; /**< Performance Monitor Counter, offset: 0xE48 */ 165 uint8_t RESERVED_21[4]; 166 __IO uint32_t PMLCA4; /**< Performance Monitor Local Control A, offset: 0xE50 */ 167 __IO uint32_t PMLCB4; /**< Performance Monitor Local Control B, offset: 0xE54 */ 168 __IO uint32_t PMC4; /**< Performance Monitor Counter, offset: 0xE58 */ 169 uint8_t RESERVED_22[4]; 170 __IO uint32_t PMLCA5; /**< Performance Monitor Local Control A, offset: 0xE60 */ 171 __IO uint32_t PMLCB5; /**< Performance Monitor Local Control B, offset: 0xE64 */ 172 __IO uint32_t PMC5; /**< Performance Monitor Counter, offset: 0xE68 */ 173 uint8_t RESERVED_23[4]; 174 __IO uint32_t PMLCA6; /**< Performance Monitor Local Control A, offset: 0xE70 */ 175 __IO uint32_t PMLCB6; /**< Performance Monitor Local Control B, offset: 0xE74 */ 176 __IO uint32_t PMC6; /**< Performance Monitor Counter, offset: 0xE78 */ 177 uint8_t RESERVED_24[4]; 178 __IO uint32_t PMLCA7; /**< Performance Monitor Local Control A, offset: 0xE80 */ 179 __IO uint32_t PMLCB7; /**< Performance Monitor Local Control B, offset: 0xE84 */ 180 __IO uint32_t PMC7; /**< Performance Monitor Counter, offset: 0xE88 */ 181 uint8_t RESERVED_25[4]; 182 __IO uint32_t PMLCA8; /**< Performance Monitor Local Control A, offset: 0xE90 */ 183 __IO uint32_t PMLCB8; /**< Performance Monitor Local Control B, offset: 0xE94 */ 184 __IO uint32_t PMC8; /**< Performance Monitor Counter, offset: 0xE98 */ 185 uint8_t RESERVED_26[4]; 186 __IO uint32_t PMLCA9; /**< Performance Monitor Local Control A, offset: 0xEA0 */ 187 __IO uint32_t PMLCB9; /**< Performance Monitor Local Control B, offset: 0xEA4 */ 188 __IO uint32_t PMC9; /**< Performance Monitor Counter, offset: 0xEA8 */ 189 uint8_t RESERVED_27[4]; 190 __IO uint32_t PMLCA10; /**< Performance Monitor Local Control A, offset: 0xEB0 */ 191 __IO uint32_t PMLCB10; /**< Performance Monitor Local Control B, offset: 0xEB4 */ 192 __IO uint32_t PMC10; /**< Performance Monitor Counter, offset: 0xEB8 */ 193 uint8_t RESERVED_28[324]; 194 __IO uint32_t ERR_EN; /**< Error Enable, offset: 0x1000 */ 195 uint8_t RESERVED_29[252]; 196 __IO uint32_t DATA_ERR_INJECT_HI; /**< Memory Data Path Error Injection Mask High, offset: 0x1100 */ 197 __IO uint32_t DATA_ERR_INJECT_LO; /**< Memory Data Path Error Injection Mask Low, offset: 0x1104 */ 198 __IO uint32_t ERR_INJECT; /**< Memory Data Path Error Injection Mask ECC, offset: 0x1108 */ 199 __IO uint32_t ADDR_ERR_INJ; /**< Address Error Inject, offset: 0x110C */ 200 uint8_t RESERVED_30[8]; 201 __IO uint32_t CAPTURE_EXT_DATA_HI; /**< Memory Extended Data Path Read Capture High, offset: 0x1118 */ 202 __IO uint32_t CAPTURE_EXT_DATA_LO; /**< Memory Extended Data Path Read Capture Low, offset: 0x111C */ 203 __IO uint32_t CAPTURE_DATA_HI; /**< Memory Data Path Read Capture High, offset: 0x1120 */ 204 __IO uint32_t CAPTURE_DATA_LO; /**< Memory Data Path Read Capture Low, offset: 0x1124 */ 205 __IO uint32_t CAPTURE_ECC; /**< Memory Data Path Read Capture ECC, offset: 0x1128 */ 206 uint8_t RESERVED_31[20]; 207 __IO uint32_t ERR_DETECT; /**< Memory Error Detect, offset: 0x1140 */ 208 __IO uint32_t ERR_DISABLE; /**< Memory Error Disable, offset: 0x1144 */ 209 __IO uint32_t ERR_INT_EN; /**< Memory Error Interrupt Enable, offset: 0x1148 */ 210 __IO uint32_t CAPTURE_ATTRIBUTES; /**< Memory Error Attributes Capture, offset: 0x114C */ 211 __IO uint32_t CAPTURE_ADDRESS; /**< Memory Error Address Capture, offset: 0x1150 */ 212 __IO uint32_t CAPTURE_EXT_ADDRESS; /**< Memory Error Extended Address Capture, offset: 0x1154 */ 213 __IO uint32_t ERR_SBE; /**< Single-Bit ECC Memory Error Management, offset: 0x1158 */ 214 uint8_t RESERVED_32[164]; 215 __IO uint32_t REG_LKSTP_CNTL; /**< Lockstep Register Control, offset: 0x1200 */ 216 uint8_t RESERVED_33[12]; 217 __IO uint32_t REG_CRC_GRP_1; /**< Register CRC Code For Group 1, offset: 0x1210 */ 218 __IO uint32_t REG_CRC_GRP_2; /**< Register CRC Code For Group 2, offset: 0x1214 */ 219 uint8_t RESERVED_34[40]; 220 __IO uint32_t ECC_REG_0; /**< ECC Region 0 Configuration, offset: 0x1240 */ 221 __IO uint32_t ECC_REG_1; /**< ECC Region 1 Configuration, offset: 0x1244 */ 222 __IO uint32_t ECC_REG_2; /**< ECC Region 2 Configuration, offset: 0x1248 */ 223 __IO uint32_t ECC_REG_3; /**< ECC Region 3 Configuration, offset: 0x124C */ 224 __IO uint32_t ECC_REG_4; /**< ECC Region 4 Configuration, offset: 0x1250 */ 225 __IO uint32_t ECC_REG_5; /**< ECC Region 5 Configuration, offset: 0x1254 */ 226 __IO uint32_t ECC_REG_6; /**< ECC Region 6 Configuration, offset: 0x1258 */ 227 __IO uint32_t ECC_REG_7; /**< ECC Region 7 Configuration, offset: 0x125C */ 228 } DDRC_Type, *DDRC_MemMapPtr; 229 230 /** Number of instances of the DDRC module. */ 231 #define DDRC_INSTANCE_COUNT (1u) 232 233 /* DDRC - Peripheral instance base addresses */ 234 /** Peripheral DDR base address */ 235 #define IP_DDR_BASE (0x72000000u) 236 /** Peripheral DDR base pointer */ 237 #define IP_DDR ((DDRC_Type *)IP_DDR_BASE) 238 /** Array initializer of DDRC peripheral base addresses */ 239 #define IP_DDRC_BASE_ADDRS { IP_DDR_BASE } 240 /** Array initializer of DDRC peripheral base pointers */ 241 #define IP_DDRC_BASE_PTRS { IP_DDR } 242 243 /* ---------------------------------------------------------------------------- 244 -- DDRC Register Masks 245 ---------------------------------------------------------------------------- */ 246 247 /*! 248 * @addtogroup DDRC_Register_Masks DDRC Register Masks 249 * @{ 250 */ 251 252 /*! @name CS_BNDS - Rank 0 Memory Bounds..Rank 1 Memory Bounds */ 253 /*! @{ */ 254 255 #define DDRC_CS_BNDS_EA_MASK (0xFFFFU) 256 #define DDRC_CS_BNDS_EA_SHIFT (0U) 257 #define DDRC_CS_BNDS_EA_WIDTH (16U) 258 #define DDRC_CS_BNDS_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_EA_SHIFT)) & DDRC_CS_BNDS_EA_MASK) 259 260 #define DDRC_CS_BNDS_SA_MASK (0xFFFF0000U) 261 #define DDRC_CS_BNDS_SA_SHIFT (16U) 262 #define DDRC_CS_BNDS_SA_WIDTH (16U) 263 #define DDRC_CS_BNDS_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_BNDS_SA_SHIFT)) & DDRC_CS_BNDS_SA_MASK) 264 /*! @} */ 265 266 /*! @name REMAP_0A - Remap Region 0A Configuration */ 267 /*! @{ */ 268 269 #define DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK (0xFFFU) 270 #define DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT (0U) 271 #define DDRC_REMAP_0A_REG_0_REMAP_ADDR_WIDTH (12U) 272 #define DDRC_REMAP_0A_REG_0_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_ADDR_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_ADDR_MASK) 273 274 #define DDRC_REMAP_0A_REG_0_REMAP_EN_MASK (0x80000000U) 275 #define DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT (31U) 276 #define DDRC_REMAP_0A_REG_0_REMAP_EN_WIDTH (1U) 277 #define DDRC_REMAP_0A_REG_0_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0A_REG_0_REMAP_EN_SHIFT)) & DDRC_REMAP_0A_REG_0_REMAP_EN_MASK) 278 /*! @} */ 279 280 /*! @name REMAP_0B - Remap Region 0B Configuration */ 281 /*! @{ */ 282 283 #define DDRC_REMAP_0B_REG_0_EA_MASK (0xFFFU) 284 #define DDRC_REMAP_0B_REG_0_EA_SHIFT (0U) 285 #define DDRC_REMAP_0B_REG_0_EA_WIDTH (12U) 286 #define DDRC_REMAP_0B_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_EA_SHIFT)) & DDRC_REMAP_0B_REG_0_EA_MASK) 287 288 #define DDRC_REMAP_0B_REG_0_SA_MASK (0xFFF0000U) 289 #define DDRC_REMAP_0B_REG_0_SA_SHIFT (16U) 290 #define DDRC_REMAP_0B_REG_0_SA_WIDTH (12U) 291 #define DDRC_REMAP_0B_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_0B_REG_0_SA_SHIFT)) & DDRC_REMAP_0B_REG_0_SA_MASK) 292 /*! @} */ 293 294 /*! @name REMAP_1A - Remap Region 1A Configuration */ 295 /*! @{ */ 296 297 #define DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK (0xFFFU) 298 #define DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT (0U) 299 #define DDRC_REMAP_1A_REG_1_REMAP_ADDR_WIDTH (12U) 300 #define DDRC_REMAP_1A_REG_1_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_ADDR_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_ADDR_MASK) 301 302 #define DDRC_REMAP_1A_REG_1_REMAP_EN_MASK (0x80000000U) 303 #define DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT (31U) 304 #define DDRC_REMAP_1A_REG_1_REMAP_EN_WIDTH (1U) 305 #define DDRC_REMAP_1A_REG_1_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1A_REG_1_REMAP_EN_SHIFT)) & DDRC_REMAP_1A_REG_1_REMAP_EN_MASK) 306 /*! @} */ 307 308 /*! @name REMAP_1B - Remap Region 1B Configuration */ 309 /*! @{ */ 310 311 #define DDRC_REMAP_1B_REG_1_EA_MASK (0xFFFU) 312 #define DDRC_REMAP_1B_REG_1_EA_SHIFT (0U) 313 #define DDRC_REMAP_1B_REG_1_EA_WIDTH (12U) 314 #define DDRC_REMAP_1B_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_EA_SHIFT)) & DDRC_REMAP_1B_REG_1_EA_MASK) 315 316 #define DDRC_REMAP_1B_REG_1_SA_MASK (0xFFF0000U) 317 #define DDRC_REMAP_1B_REG_1_SA_SHIFT (16U) 318 #define DDRC_REMAP_1B_REG_1_SA_WIDTH (12U) 319 #define DDRC_REMAP_1B_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_1B_REG_1_SA_SHIFT)) & DDRC_REMAP_1B_REG_1_SA_MASK) 320 /*! @} */ 321 322 /*! @name REMAP_2A - Remap Region 2A Configuration */ 323 /*! @{ */ 324 325 #define DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK (0xFFFU) 326 #define DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT (0U) 327 #define DDRC_REMAP_2A_REG_2_REMAP_ADDR_WIDTH (12U) 328 #define DDRC_REMAP_2A_REG_2_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_ADDR_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_ADDR_MASK) 329 330 #define DDRC_REMAP_2A_REG_2_REMAP_EN_MASK (0x80000000U) 331 #define DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT (31U) 332 #define DDRC_REMAP_2A_REG_2_REMAP_EN_WIDTH (1U) 333 #define DDRC_REMAP_2A_REG_2_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2A_REG_2_REMAP_EN_SHIFT)) & DDRC_REMAP_2A_REG_2_REMAP_EN_MASK) 334 /*! @} */ 335 336 /*! @name REMAP_2B - Remap Region 2B Configuration */ 337 /*! @{ */ 338 339 #define DDRC_REMAP_2B_REG_2_EA_MASK (0xFFFU) 340 #define DDRC_REMAP_2B_REG_2_EA_SHIFT (0U) 341 #define DDRC_REMAP_2B_REG_2_EA_WIDTH (12U) 342 #define DDRC_REMAP_2B_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_EA_SHIFT)) & DDRC_REMAP_2B_REG_2_EA_MASK) 343 344 #define DDRC_REMAP_2B_REG_2_SA_MASK (0xFFF0000U) 345 #define DDRC_REMAP_2B_REG_2_SA_SHIFT (16U) 346 #define DDRC_REMAP_2B_REG_2_SA_WIDTH (12U) 347 #define DDRC_REMAP_2B_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_2B_REG_2_SA_SHIFT)) & DDRC_REMAP_2B_REG_2_SA_MASK) 348 /*! @} */ 349 350 /*! @name REMAP_3A - Remap Region 3A Configuration */ 351 /*! @{ */ 352 353 #define DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK (0xFFFU) 354 #define DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT (0U) 355 #define DDRC_REMAP_3A_REG_3_REMAP_ADDR_WIDTH (12U) 356 #define DDRC_REMAP_3A_REG_3_REMAP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_ADDR_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_ADDR_MASK) 357 358 #define DDRC_REMAP_3A_REG_3_REMAP_EN_MASK (0x80000000U) 359 #define DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT (31U) 360 #define DDRC_REMAP_3A_REG_3_REMAP_EN_WIDTH (1U) 361 #define DDRC_REMAP_3A_REG_3_REMAP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3A_REG_3_REMAP_EN_SHIFT)) & DDRC_REMAP_3A_REG_3_REMAP_EN_MASK) 362 /*! @} */ 363 364 /*! @name REMAP_3B - Remap Region 3B Configuration */ 365 /*! @{ */ 366 367 #define DDRC_REMAP_3B_REG_3_EA_MASK (0xFFFU) 368 #define DDRC_REMAP_3B_REG_3_EA_SHIFT (0U) 369 #define DDRC_REMAP_3B_REG_3_EA_WIDTH (12U) 370 #define DDRC_REMAP_3B_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_EA_SHIFT)) & DDRC_REMAP_3B_REG_3_EA_MASK) 371 372 #define DDRC_REMAP_3B_REG_3_SA_MASK (0xFFF0000U) 373 #define DDRC_REMAP_3B_REG_3_SA_SHIFT (16U) 374 #define DDRC_REMAP_3B_REG_3_SA_WIDTH (12U) 375 #define DDRC_REMAP_3B_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REMAP_3B_REG_3_SA_SHIFT)) & DDRC_REMAP_3B_REG_3_SA_MASK) 376 /*! @} */ 377 378 /*! @name DDR_ADDR_DEC_0 - DDRC Address Decode 0 */ 379 /*! @{ */ 380 381 #define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK (0xFCU) 382 #define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT (2U) 383 #define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_WIDTH (6U) 384 #define DDRC_DDR_ADDR_DEC_0_ROW14_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW14_OVRD_MASK) 385 386 #define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK (0xFC00U) 387 #define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT (10U) 388 #define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_WIDTH (6U) 389 #define DDRC_DDR_ADDR_DEC_0_ROW15_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW15_OVRD_MASK) 390 391 #define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK (0xFC0000U) 392 #define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT (18U) 393 #define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_WIDTH (6U) 394 #define DDRC_DDR_ADDR_DEC_0_ROW16_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW16_OVRD_MASK) 395 396 #define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK (0xFC000000U) 397 #define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT (26U) 398 #define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_WIDTH (6U) 399 #define DDRC_DDR_ADDR_DEC_0_ROW17_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_0_ROW17_OVRD_MASK) 400 /*! @} */ 401 402 /*! @name DDR_ADDR_DEC_1 - DDRC Address Decode 1 */ 403 /*! @{ */ 404 405 #define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK (0xFCU) 406 #define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT (2U) 407 #define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_WIDTH (6U) 408 #define DDRC_DDR_ADDR_DEC_1_ROW10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW10_OVRD_MASK) 409 410 #define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK (0xFC00U) 411 #define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT (10U) 412 #define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_WIDTH (6U) 413 #define DDRC_DDR_ADDR_DEC_1_ROW11_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW11_OVRD_MASK) 414 415 #define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK (0xFC0000U) 416 #define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT (18U) 417 #define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_WIDTH (6U) 418 #define DDRC_DDR_ADDR_DEC_1_ROW12_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW12_OVRD_MASK) 419 420 #define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK (0xFC000000U) 421 #define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT (26U) 422 #define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_WIDTH (6U) 423 #define DDRC_DDR_ADDR_DEC_1_ROW13_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_1_ROW13_OVRD_MASK) 424 /*! @} */ 425 426 /*! @name DDR_ADDR_DEC_2 - DDRC Address Decode 2 */ 427 /*! @{ */ 428 429 #define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK (0xFCU) 430 #define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT (2U) 431 #define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_WIDTH (6U) 432 #define DDRC_DDR_ADDR_DEC_2_ROW6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW6_OVRD_MASK) 433 434 #define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK (0xFC00U) 435 #define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT (10U) 436 #define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_WIDTH (6U) 437 #define DDRC_DDR_ADDR_DEC_2_ROW7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW7_OVRD_MASK) 438 439 #define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK (0xFC0000U) 440 #define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT (18U) 441 #define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_WIDTH (6U) 442 #define DDRC_DDR_ADDR_DEC_2_ROW8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW8_OVRD_MASK) 443 444 #define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK (0xFC000000U) 445 #define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT (26U) 446 #define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_WIDTH (6U) 447 #define DDRC_DDR_ADDR_DEC_2_ROW9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_2_ROW9_OVRD_MASK) 448 /*! @} */ 449 450 /*! @name DDR_ADDR_DEC_3 - DDRC Address Decode 3 */ 451 /*! @{ */ 452 453 #define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK (0xFCU) 454 #define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT (2U) 455 #define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_WIDTH (6U) 456 #define DDRC_DDR_ADDR_DEC_3_ROW2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW2_OVRD_MASK) 457 458 #define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK (0xFC00U) 459 #define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT (10U) 460 #define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_WIDTH (6U) 461 #define DDRC_DDR_ADDR_DEC_3_ROW3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW3_OVRD_MASK) 462 463 #define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK (0xFC0000U) 464 #define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT (18U) 465 #define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_WIDTH (6U) 466 #define DDRC_DDR_ADDR_DEC_3_ROW4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW4_OVRD_MASK) 467 468 #define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK (0xFC000000U) 469 #define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT (26U) 470 #define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_WIDTH (6U) 471 #define DDRC_DDR_ADDR_DEC_3_ROW5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_3_ROW5_OVRD_MASK) 472 /*! @} */ 473 474 /*! @name DDR_ADDR_DEC_4 - DDRC Address Decode 4 */ 475 /*! @{ */ 476 477 #define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK (0xFCU) 478 #define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT (2U) 479 #define DDRC_DDR_ADDR_DEC_4_COL9_OVRD_WIDTH (6U) 480 #define DDRC_DDR_ADDR_DEC_4_COL9_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL9_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL9_OVRD_MASK) 481 482 #define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK (0xFC00U) 483 #define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT (10U) 484 #define DDRC_DDR_ADDR_DEC_4_COL10_OVRD_WIDTH (6U) 485 #define DDRC_DDR_ADDR_DEC_4_COL10_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_COL10_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_COL10_OVRD_MASK) 486 487 #define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK (0xFC0000U) 488 #define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT (18U) 489 #define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_WIDTH (6U) 490 #define DDRC_DDR_ADDR_DEC_4_ROW0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW0_OVRD_MASK) 491 492 #define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK (0xFC000000U) 493 #define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT (26U) 494 #define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_WIDTH (6U) 495 #define DDRC_DDR_ADDR_DEC_4_ROW1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_4_ROW1_OVRD_MASK) 496 /*! @} */ 497 498 /*! @name DDR_ADDR_DEC_5 - DDRC Address Decode 5 */ 499 /*! @{ */ 500 501 #define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK (0xFCU) 502 #define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT (2U) 503 #define DDRC_DDR_ADDR_DEC_5_COL5_OVRD_WIDTH (6U) 504 #define DDRC_DDR_ADDR_DEC_5_COL5_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL5_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL5_OVRD_MASK) 505 506 #define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK (0xFC00U) 507 #define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT (10U) 508 #define DDRC_DDR_ADDR_DEC_5_COL6_OVRD_WIDTH (6U) 509 #define DDRC_DDR_ADDR_DEC_5_COL6_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL6_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL6_OVRD_MASK) 510 511 #define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK (0xFC0000U) 512 #define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT (18U) 513 #define DDRC_DDR_ADDR_DEC_5_COL7_OVRD_WIDTH (6U) 514 #define DDRC_DDR_ADDR_DEC_5_COL7_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL7_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL7_OVRD_MASK) 515 516 #define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK (0xFC000000U) 517 #define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT (26U) 518 #define DDRC_DDR_ADDR_DEC_5_COL8_OVRD_WIDTH (6U) 519 #define DDRC_DDR_ADDR_DEC_5_COL8_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_5_COL8_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_5_COL8_OVRD_MASK) 520 /*! @} */ 521 522 /*! @name DDR_ADDR_DEC_6 - DDRC Address Decode 6 */ 523 /*! @{ */ 524 525 #define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK (0xFCU) 526 #define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT (2U) 527 #define DDRC_DDR_ADDR_DEC_6_COL1_OVRD_WIDTH (6U) 528 #define DDRC_DDR_ADDR_DEC_6_COL1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL1_OVRD_MASK) 529 530 #define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK (0xFC00U) 531 #define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT (10U) 532 #define DDRC_DDR_ADDR_DEC_6_COL2_OVRD_WIDTH (6U) 533 #define DDRC_DDR_ADDR_DEC_6_COL2_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL2_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL2_OVRD_MASK) 534 535 #define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK (0xFC0000U) 536 #define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT (18U) 537 #define DDRC_DDR_ADDR_DEC_6_COL3_OVRD_WIDTH (6U) 538 #define DDRC_DDR_ADDR_DEC_6_COL3_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL3_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL3_OVRD_MASK) 539 540 #define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK (0xFC000000U) 541 #define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT (26U) 542 #define DDRC_DDR_ADDR_DEC_6_COL4_OVRD_WIDTH (6U) 543 #define DDRC_DDR_ADDR_DEC_6_COL4_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_6_COL4_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_6_COL4_OVRD_MASK) 544 /*! @} */ 545 546 /*! @name DDR_ADDR_DEC_7 - DDRC Address Decode 7 */ 547 /*! @{ */ 548 549 #define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK (0xFCU) 550 #define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT (2U) 551 #define DDRC_DDR_ADDR_DEC_7_CID1_OVRD_WIDTH (6U) 552 #define DDRC_DDR_ADDR_DEC_7_CID1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_CID1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_CID1_OVRD_MASK) 553 554 #define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK (0xFC00U) 555 #define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT (10U) 556 #define DDRC_DDR_ADDR_DEC_7_BA0_OVRD_WIDTH (6U) 557 #define DDRC_DDR_ADDR_DEC_7_BA0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA0_OVRD_MASK) 558 559 #define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK (0xFC0000U) 560 #define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT (18U) 561 #define DDRC_DDR_ADDR_DEC_7_BA1_OVRD_WIDTH (6U) 562 #define DDRC_DDR_ADDR_DEC_7_BA1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_BA1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_BA1_OVRD_MASK) 563 564 #define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK (0xFC000000U) 565 #define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT (26U) 566 #define DDRC_DDR_ADDR_DEC_7_COL0_OVRD_WIDTH (6U) 567 #define DDRC_DDR_ADDR_DEC_7_COL0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_7_COL0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_7_COL0_OVRD_MASK) 568 /*! @} */ 569 570 /*! @name DDR_ADDR_DEC_8 - DDRC Address Decode 8 */ 571 /*! @{ */ 572 573 #define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK (0xFCU) 574 #define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT (2U) 575 #define DDRC_DDR_ADDR_DEC_8_BG1_OVRD_WIDTH (6U) 576 #define DDRC_DDR_ADDR_DEC_8_BG1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_BG1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_BG1_OVRD_MASK) 577 578 #define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK (0xFC00U) 579 #define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT (10U) 580 #define DDRC_DDR_ADDR_DEC_8_CS0_OVRD_WIDTH (6U) 581 #define DDRC_DDR_ADDR_DEC_8_CS0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS0_OVRD_MASK) 582 583 #define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK (0xFC0000U) 584 #define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT (18U) 585 #define DDRC_DDR_ADDR_DEC_8_CS1_OVRD_WIDTH (6U) 586 #define DDRC_DDR_ADDR_DEC_8_CS1_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CS1_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CS1_OVRD_MASK) 587 588 #define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK (0xFC000000U) 589 #define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT (26U) 590 #define DDRC_DDR_ADDR_DEC_8_CID0_OVRD_WIDTH (6U) 591 #define DDRC_DDR_ADDR_DEC_8_CID0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_8_CID0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_8_CID0_OVRD_MASK) 592 /*! @} */ 593 594 /*! @name DDR_ADDR_DEC_9 - DDRC Address Decode 9 */ 595 /*! @{ */ 596 597 #define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK (0x1U) 598 #define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT (0U) 599 #define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_WIDTH (1U) 600 #define DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_ADDR_DEC_OVRD_MASK) 601 602 #define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK (0xFC000000U) 603 #define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT (26U) 604 #define DDRC_DDR_ADDR_DEC_9_BG0_OVRD_WIDTH (6U) 605 #define DDRC_DDR_ADDR_DEC_9_BG0_OVRD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ADDR_DEC_9_BG0_OVRD_SHIFT)) & DDRC_DDR_ADDR_DEC_9_BG0_OVRD_MASK) 606 /*! @} */ 607 608 /*! @name CS_CONFIG - Rank 0 Configuration..Rank 1 Configuration */ 609 /*! @{ */ 610 611 #define DDRC_CS_CONFIG_COL_BITS_CS_MASK (0x7U) 612 #define DDRC_CS_CONFIG_COL_BITS_CS_SHIFT (0U) 613 #define DDRC_CS_CONFIG_COL_BITS_CS_WIDTH (3U) 614 #define DDRC_CS_CONFIG_COL_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_COL_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_COL_BITS_CS_MASK) 615 616 #define DDRC_CS_CONFIG_BG_BITS_CS_MASK (0x30U) 617 #define DDRC_CS_CONFIG_BG_BITS_CS_SHIFT (4U) 618 #define DDRC_CS_CONFIG_BG_BITS_CS_WIDTH (2U) 619 #define DDRC_CS_CONFIG_BG_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_BG_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_BG_BITS_CS_MASK) 620 621 #define DDRC_CS_CONFIG_ROW_BITS_CS_MASK (0x700U) 622 #define DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT (8U) 623 #define DDRC_CS_CONFIG_ROW_BITS_CS_WIDTH (3U) 624 #define DDRC_CS_CONFIG_ROW_BITS_CS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_ROW_BITS_CS_SHIFT)) & DDRC_CS_CONFIG_ROW_BITS_CS_MASK) 625 626 #define DDRC_CS_CONFIG_AP_EN_MASK (0x800000U) 627 #define DDRC_CS_CONFIG_AP_EN_SHIFT (23U) 628 #define DDRC_CS_CONFIG_AP_EN_WIDTH (1U) 629 #define DDRC_CS_CONFIG_AP_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_AP_EN_SHIFT)) & DDRC_CS_CONFIG_AP_EN_MASK) 630 631 #define DDRC_CS_CONFIG_CS_EN_MASK (0x80000000U) 632 #define DDRC_CS_CONFIG_CS_EN_SHIFT (31U) 633 #define DDRC_CS_CONFIG_CS_EN_WIDTH (1U) 634 #define DDRC_CS_CONFIG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CS_CONFIG_CS_EN_SHIFT)) & DDRC_CS_CONFIG_CS_EN_MASK) 635 /*! @} */ 636 637 /*! @name TIMING_CFG_3 - DDR SDRAM Timing Configuration 3 */ 638 /*! @{ */ 639 640 #define DDRC_TIMING_CFG_3_EXT_WRTORD_MASK (0x1U) 641 #define DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT (0U) 642 #define DDRC_TIMING_CFG_3_EXT_WRTORD_WIDTH (1U) 643 #define DDRC_TIMING_CFG_3_EXT_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRTORD_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRTORD_MASK) 644 645 #define DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK (0x2U) 646 #define DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT (1U) 647 #define DDRC_TIMING_CFG_3_EXT_ACTTOACT_WIDTH (1U) 648 #define DDRC_TIMING_CFG_3_EXT_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOACT_MASK) 649 650 #define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK (0x8U) 651 #define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT (3U) 652 #define DDRC_TIMING_CFG_3_EXT_FOUR_ACT_WIDTH (1U) 653 #define DDRC_TIMING_CFG_3_EXT_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_FOUR_ACT_MASK) 654 655 #define DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK (0x30U) 656 #define DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT (4U) 657 #define DDRC_TIMING_CFG_3_EXT_CKE_PLS_WIDTH (2U) 658 #define DDRC_TIMING_CFG_3_EXT_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CKE_PLS_MASK) 659 660 #define DDRC_TIMING_CFG_3_EXT_WRREC_MASK (0x300U) 661 #define DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT (8U) 662 #define DDRC_TIMING_CFG_3_EXT_WRREC_WIDTH (2U) 663 #define DDRC_TIMING_CFG_3_EXT_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WRREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WRREC_MASK) 664 665 #define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK (0x800U) 666 #define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT (11U) 667 #define DDRC_TIMING_CFG_3_EXT_WR_LAT_2_WIDTH (1U) 668 #define DDRC_TIMING_CFG_3_EXT_WR_LAT_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_WR_LAT_2_SHIFT)) & DDRC_TIMING_CFG_3_EXT_WR_LAT_2_MASK) 669 670 #define DDRC_TIMING_CFG_3_EXT_CASLAT_MASK (0x7000U) 671 #define DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT (12U) 672 #define DDRC_TIMING_CFG_3_EXT_CASLAT_WIDTH (3U) 673 #define DDRC_TIMING_CFG_3_EXT_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_CASLAT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_CASLAT_MASK) 674 675 #define DDRC_TIMING_CFG_3_EXT_REFREC_MASK (0x3F0000U) 676 #define DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT (16U) 677 #define DDRC_TIMING_CFG_3_EXT_REFREC_WIDTH (6U) 678 #define DDRC_TIMING_CFG_3_EXT_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_REFREC_SHIFT)) & DDRC_TIMING_CFG_3_EXT_REFREC_MASK) 679 680 #define DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK (0xC00000U) 681 #define DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT (22U) 682 #define DDRC_TIMING_CFG_3_EXT_ACTTORW_WIDTH (2U) 683 #define DDRC_TIMING_CFG_3_EXT_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTORW_MASK) 684 685 #define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK (0x7000000U) 686 #define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT (24U) 687 #define DDRC_TIMING_CFG_3_EXT_ACTTOPRE_WIDTH (3U) 688 #define DDRC_TIMING_CFG_3_EXT_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_3_EXT_ACTTOPRE_MASK) 689 690 #define DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK (0x30000000U) 691 #define DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT (28U) 692 #define DDRC_TIMING_CFG_3_EXT_PRETOACT_WIDTH (2U) 693 #define DDRC_TIMING_CFG_3_EXT_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_3_EXT_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_3_EXT_PRETOACT_MASK) 694 /*! @} */ 695 696 /*! @name TIMING_CFG_0 - DDR SDRAM Timing Configuration 0 */ 697 /*! @{ */ 698 699 #define DDRC_TIMING_CFG_0_MRS_CYC_MASK (0x3FU) 700 #define DDRC_TIMING_CFG_0_MRS_CYC_SHIFT (0U) 701 #define DDRC_TIMING_CFG_0_MRS_CYC_WIDTH (6U) 702 #define DDRC_TIMING_CFG_0_MRS_CYC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_MRS_CYC_SHIFT)) & DDRC_TIMING_CFG_0_MRS_CYC_MASK) 703 704 #define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK (0x1000U) 705 #define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT (12U) 706 #define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_WIDTH (1U) 707 #define DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_ACT_PD_EXIT_MASK) 708 709 #define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK (0xC000U) 710 #define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT (14U) 711 #define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_WIDTH (2U) 712 #define DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_EXT_PRE_PD_EXIT_MASK) 713 714 #define DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK (0xF0000U) 715 #define DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT (16U) 716 #define DDRC_TIMING_CFG_0_PRE_PD_EXIT_WIDTH (4U) 717 #define DDRC_TIMING_CFG_0_PRE_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_PRE_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_PRE_PD_EXIT_MASK) 718 719 #define DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK (0xF00000U) 720 #define DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT (20U) 721 #define DDRC_TIMING_CFG_0_ACT_PD_EXIT_WIDTH (4U) 722 #define DDRC_TIMING_CFG_0_ACT_PD_EXIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_ACT_PD_EXIT_SHIFT)) & DDRC_TIMING_CFG_0_ACT_PD_EXIT_MASK) 723 724 #define DDRC_TIMING_CFG_0_WWT_MASK (0x3000000U) 725 #define DDRC_TIMING_CFG_0_WWT_SHIFT (24U) 726 #define DDRC_TIMING_CFG_0_WWT_WIDTH (2U) 727 #define DDRC_TIMING_CFG_0_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WWT_SHIFT)) & DDRC_TIMING_CFG_0_WWT_MASK) 728 729 #define DDRC_TIMING_CFG_0_RRT_MASK (0xC000000U) 730 #define DDRC_TIMING_CFG_0_RRT_SHIFT (26U) 731 #define DDRC_TIMING_CFG_0_RRT_WIDTH (2U) 732 #define DDRC_TIMING_CFG_0_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RRT_SHIFT)) & DDRC_TIMING_CFG_0_RRT_MASK) 733 734 #define DDRC_TIMING_CFG_0_WRT_MASK (0x30000000U) 735 #define DDRC_TIMING_CFG_0_WRT_SHIFT (28U) 736 #define DDRC_TIMING_CFG_0_WRT_WIDTH (2U) 737 #define DDRC_TIMING_CFG_0_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_WRT_SHIFT)) & DDRC_TIMING_CFG_0_WRT_MASK) 738 739 #define DDRC_TIMING_CFG_0_RWT_MASK (0xC0000000U) 740 #define DDRC_TIMING_CFG_0_RWT_SHIFT (30U) 741 #define DDRC_TIMING_CFG_0_RWT_WIDTH (2U) 742 #define DDRC_TIMING_CFG_0_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_0_RWT_SHIFT)) & DDRC_TIMING_CFG_0_RWT_MASK) 743 /*! @} */ 744 745 /*! @name TIMING_CFG_1 - DDR SDRAM Timing Configuration 1 */ 746 /*! @{ */ 747 748 #define DDRC_TIMING_CFG_1_WRTORD_MASK (0xFU) 749 #define DDRC_TIMING_CFG_1_WRTORD_SHIFT (0U) 750 #define DDRC_TIMING_CFG_1_WRTORD_WIDTH (4U) 751 #define DDRC_TIMING_CFG_1_WRTORD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRTORD_SHIFT)) & DDRC_TIMING_CFG_1_WRTORD_MASK) 752 753 #define DDRC_TIMING_CFG_1_ACTTOACT_MASK (0xF0U) 754 #define DDRC_TIMING_CFG_1_ACTTOACT_SHIFT (4U) 755 #define DDRC_TIMING_CFG_1_ACTTOACT_WIDTH (4U) 756 #define DDRC_TIMING_CFG_1_ACTTOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOACT_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOACT_MASK) 757 758 #define DDRC_TIMING_CFG_1_WRREC_MASK (0xF00U) 759 #define DDRC_TIMING_CFG_1_WRREC_SHIFT (8U) 760 #define DDRC_TIMING_CFG_1_WRREC_WIDTH (4U) 761 #define DDRC_TIMING_CFG_1_WRREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_WRREC_SHIFT)) & DDRC_TIMING_CFG_1_WRREC_MASK) 762 763 #define DDRC_TIMING_CFG_1_REFREC_MASK (0xF000U) 764 #define DDRC_TIMING_CFG_1_REFREC_SHIFT (12U) 765 #define DDRC_TIMING_CFG_1_REFREC_WIDTH (4U) 766 #define DDRC_TIMING_CFG_1_REFREC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_REFREC_SHIFT)) & DDRC_TIMING_CFG_1_REFREC_MASK) 767 768 #define DDRC_TIMING_CFG_1_CASLAT_MASK (0xE0000U) 769 #define DDRC_TIMING_CFG_1_CASLAT_SHIFT (17U) 770 #define DDRC_TIMING_CFG_1_CASLAT_WIDTH (3U) 771 #define DDRC_TIMING_CFG_1_CASLAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_CASLAT_SHIFT)) & DDRC_TIMING_CFG_1_CASLAT_MASK) 772 773 #define DDRC_TIMING_CFG_1_ACTTORW_MASK (0xF00000U) 774 #define DDRC_TIMING_CFG_1_ACTTORW_SHIFT (20U) 775 #define DDRC_TIMING_CFG_1_ACTTORW_WIDTH (4U) 776 #define DDRC_TIMING_CFG_1_ACTTORW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTORW_SHIFT)) & DDRC_TIMING_CFG_1_ACTTORW_MASK) 777 778 #define DDRC_TIMING_CFG_1_ACTTOPRE_MASK (0xF000000U) 779 #define DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT (24U) 780 #define DDRC_TIMING_CFG_1_ACTTOPRE_WIDTH (4U) 781 #define DDRC_TIMING_CFG_1_ACTTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_ACTTOPRE_SHIFT)) & DDRC_TIMING_CFG_1_ACTTOPRE_MASK) 782 783 #define DDRC_TIMING_CFG_1_PRETOACT_MASK (0xF0000000U) 784 #define DDRC_TIMING_CFG_1_PRETOACT_SHIFT (28U) 785 #define DDRC_TIMING_CFG_1_PRETOACT_WIDTH (4U) 786 #define DDRC_TIMING_CFG_1_PRETOACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_1_PRETOACT_SHIFT)) & DDRC_TIMING_CFG_1_PRETOACT_MASK) 787 /*! @} */ 788 789 /*! @name TIMING_CFG_2 - DDR SDRAM Timing Configuration 2 */ 790 /*! @{ */ 791 792 #define DDRC_TIMING_CFG_2_FOUR_ACT_MASK (0x3FU) 793 #define DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT (0U) 794 #define DDRC_TIMING_CFG_2_FOUR_ACT_WIDTH (6U) 795 #define DDRC_TIMING_CFG_2_FOUR_ACT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_FOUR_ACT_SHIFT)) & DDRC_TIMING_CFG_2_FOUR_ACT_MASK) 796 797 #define DDRC_TIMING_CFG_2_CKE_PLS_MASK (0x1C0U) 798 #define DDRC_TIMING_CFG_2_CKE_PLS_SHIFT (6U) 799 #define DDRC_TIMING_CFG_2_CKE_PLS_WIDTH (3U) 800 #define DDRC_TIMING_CFG_2_CKE_PLS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_CKE_PLS_SHIFT)) & DDRC_TIMING_CFG_2_CKE_PLS_MASK) 801 802 #define DDRC_TIMING_CFG_2_RD_TO_PRE_MASK (0x3E000U) 803 #define DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT (13U) 804 #define DDRC_TIMING_CFG_2_RD_TO_PRE_WIDTH (5U) 805 #define DDRC_TIMING_CFG_2_RD_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_RD_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_2_RD_TO_PRE_MASK) 806 807 #define DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK (0x40000U) 808 #define DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT (18U) 809 #define DDRC_TIMING_CFG_2_EXT_WR_LAT_WIDTH (1U) 810 #define DDRC_TIMING_CFG_2_EXT_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_EXT_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_EXT_WR_LAT_MASK) 811 812 #define DDRC_TIMING_CFG_2_WR_LAT_MASK (0x780000U) 813 #define DDRC_TIMING_CFG_2_WR_LAT_SHIFT (19U) 814 #define DDRC_TIMING_CFG_2_WR_LAT_WIDTH (4U) 815 #define DDRC_TIMING_CFG_2_WR_LAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_WR_LAT_SHIFT)) & DDRC_TIMING_CFG_2_WR_LAT_MASK) 816 817 #define DDRC_TIMING_CFG_2_DERATE_VAL_MASK (0xF0000000U) 818 #define DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT (28U) 819 #define DDRC_TIMING_CFG_2_DERATE_VAL_WIDTH (4U) 820 #define DDRC_TIMING_CFG_2_DERATE_VAL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_2_DERATE_VAL_SHIFT)) & DDRC_TIMING_CFG_2_DERATE_VAL_MASK) 821 /*! @} */ 822 823 /*! @name DDR_SDRAM_CFG - DDR SDRAM Control Configuration */ 824 /*! @{ */ 825 826 #define DDRC_DDR_SDRAM_CFG_BI_MASK (0x1U) 827 #define DDRC_DDR_SDRAM_CFG_BI_SHIFT (0U) 828 #define DDRC_DDR_SDRAM_CFG_BI_WIDTH (1U) 829 #define DDRC_DDR_SDRAM_CFG_BI(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BI_SHIFT)) & DDRC_DDR_SDRAM_CFG_BI_MASK) 830 831 #define DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK (0x2U) 832 #define DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT (1U) 833 #define DDRC_DDR_SDRAM_CFG_MEM_HALT_WIDTH (1U) 834 #define DDRC_DDR_SDRAM_CFG_MEM_HALT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_HALT_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_HALT_MASK) 835 836 #define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK (0x7F00U) 837 #define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT (8U) 838 #define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_WIDTH (7U) 839 #define DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_SHIFT)) & DDRC_DDR_SDRAM_CFG_BA_INTLV_CTL_MASK) 840 841 #define DDRC_DDR_SDRAM_CFG_DBW_MASK (0x180000U) 842 #define DDRC_DDR_SDRAM_CFG_DBW_SHIFT (19U) 843 #define DDRC_DDR_SDRAM_CFG_DBW_WIDTH (2U) 844 #define DDRC_DDR_SDRAM_CFG_DBW(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DBW_SHIFT)) & DDRC_DDR_SDRAM_CFG_DBW_MASK) 845 846 #define DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK (0x200000U) 847 #define DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT (21U) 848 #define DDRC_DDR_SDRAM_CFG_DYN_PWR_WIDTH (1U) 849 #define DDRC_DDR_SDRAM_CFG_DYN_PWR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_DYN_PWR_SHIFT)) & DDRC_DDR_SDRAM_CFG_DYN_PWR_MASK) 850 851 #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK (0x7000000U) 852 #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT (24U) 853 #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_WIDTH (3U) 854 #define DDRC_DDR_SDRAM_CFG_SDRAM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_SHIFT)) & DDRC_DDR_SDRAM_CFG_SDRAM_TYPE_MASK) 855 856 #define DDRC_DDR_SDRAM_CFG_SREN_MASK (0x40000000U) 857 #define DDRC_DDR_SDRAM_CFG_SREN_SHIFT (30U) 858 #define DDRC_DDR_SDRAM_CFG_SREN_WIDTH (1U) 859 #define DDRC_DDR_SDRAM_CFG_SREN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_SREN_SHIFT)) & DDRC_DDR_SDRAM_CFG_SREN_MASK) 860 861 #define DDRC_DDR_SDRAM_CFG_MEM_EN_MASK (0x80000000U) 862 #define DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT (31U) 863 #define DDRC_DDR_SDRAM_CFG_MEM_EN_WIDTH (1U) 864 #define DDRC_DDR_SDRAM_CFG_MEM_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_MEM_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_MEM_EN_MASK) 865 /*! @} */ 866 867 /*! @name DDR_SDRAM_CFG_2 - DDR SDRAM Control Configuration 2 */ 868 /*! @{ */ 869 870 #define DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK (0x10U) 871 #define DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT (4U) 872 #define DDRC_DDR_SDRAM_CFG_2_D_INIT_WIDTH (1U) 873 #define DDRC_DDR_SDRAM_CFG_2_D_INIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_D_INIT_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_D_INIT_MASK) 874 875 #define DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK (0xF000U) 876 #define DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT (12U) 877 #define DDRC_DDR_SDRAM_CFG_2_NUM_PR_WIDTH (4U) 878 #define DDRC_DDR_SDRAM_CFG_2_NUM_PR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_NUM_PR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_NUM_PR_MASK) 879 880 #define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK (0xF000000U) 881 #define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT (24U) 882 #define DDRC_DDR_SDRAM_CFG_2_MCK_DIS_WIDTH (4U) 883 #define DDRC_DDR_SDRAM_CFG_2_MCK_DIS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_MCK_DIS_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_MCK_DIS_MASK) 884 885 #define DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK (0x80000000U) 886 #define DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT (31U) 887 #define DDRC_DDR_SDRAM_CFG_2_FRC_SR_WIDTH (1U) 888 #define DDRC_DDR_SDRAM_CFG_2_FRC_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_2_FRC_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_2_FRC_SR_MASK) 889 /*! @} */ 890 891 /*! @name DDR_SDRAM_MD_CNTL - DDR SDRAM Mode Control */ 892 /*! @{ */ 893 894 #define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK (0x3FFFFU) 895 #define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT (0U) 896 #define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_WIDTH (18U) 897 #define DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_VALUE_MASK) 898 899 #define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK (0x300000U) 900 #define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT (20U) 901 #define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_WIDTH (2U) 902 #define DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CKE_CNTL_MASK) 903 904 #define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK (0x400000U) 905 #define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT (22U) 906 #define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_WIDTH (1U) 907 #define DDRC_DDR_SDRAM_MD_CNTL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_PRE_MASK) 908 909 #define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK (0x800000U) 910 #define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT (23U) 911 #define DDRC_DDR_SDRAM_MD_CNTL_SET_REF_WIDTH (1U) 912 #define DDRC_DDR_SDRAM_MD_CNTL_SET_REF(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_SET_REF_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_SET_REF_MASK) 913 914 #define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK (0xF000000U) 915 #define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT (24U) 916 #define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_WIDTH (4U) 917 #define DDRC_DDR_SDRAM_MD_CNTL_MD_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_SEL_MASK) 918 919 #define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK (0x70000000U) 920 #define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT (28U) 921 #define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_WIDTH (3U) 922 #define DDRC_DDR_SDRAM_MD_CNTL_CS_SEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_CS_SEL_MASK) 923 924 #define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK (0x80000000U) 925 #define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT (31U) 926 #define DDRC_DDR_SDRAM_MD_CNTL_MD_EN_WIDTH (1U) 927 #define DDRC_DDR_SDRAM_MD_CNTL_MD_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_MD_CNTL_MD_EN_SHIFT)) & DDRC_DDR_SDRAM_MD_CNTL_MD_EN_MASK) 928 /*! @} */ 929 930 /*! @name DDR_SDRAM_INTERVAL - DDR SDRAM Interval Configuration */ 931 /*! @{ */ 932 933 #define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK (0x3FFFU) 934 #define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT (0U) 935 #define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_WIDTH (14U) 936 #define DDRC_DDR_SDRAM_INTERVAL_BSTOPRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_BSTOPRE_MASK) 937 938 #define DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK (0xFFFF0000U) 939 #define DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT (16U) 940 #define DDRC_DDR_SDRAM_INTERVAL_REFINT_WIDTH (16U) 941 #define DDRC_DDR_SDRAM_INTERVAL_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_INTERVAL_REFINT_SHIFT)) & DDRC_DDR_SDRAM_INTERVAL_REFINT_MASK) 942 /*! @} */ 943 944 /*! @name DDR_DATA_INIT - DDR SDRAM Data Initialization */ 945 /*! @{ */ 946 947 #define DDRC_DDR_DATA_INIT_INIT_VALUE_MASK (0xFFFFFFFFU) 948 #define DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT (0U) 949 #define DDRC_DDR_DATA_INIT_INIT_VALUE_WIDTH (32U) 950 #define DDRC_DDR_DATA_INIT_INIT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_DATA_INIT_INIT_VALUE_SHIFT)) & DDRC_DDR_DATA_INIT_INIT_VALUE_MASK) 951 /*! @} */ 952 953 /*! @name TIMING_CFG_4 - DDR SDRAM Timing Configuration 4 */ 954 /*! @{ */ 955 956 #define DDRC_TIMING_CFG_4_DLL_LOCK_MASK (0x3U) 957 #define DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT (0U) 958 #define DDRC_TIMING_CFG_4_DLL_LOCK_WIDTH (2U) 959 #define DDRC_TIMING_CFG_4_DLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_DLL_LOCK_SHIFT)) & DDRC_TIMING_CFG_4_DLL_LOCK_MASK) 960 961 #define DDRC_TIMING_CFG_4_EXT_REFINT_MASK (0x10U) 962 #define DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT (4U) 963 #define DDRC_TIMING_CFG_4_EXT_REFINT_WIDTH (1U) 964 #define DDRC_TIMING_CFG_4_EXT_REFINT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_REFINT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_REFINT_MASK) 965 966 #define DDRC_TIMING_CFG_4_EXT_WWT_MASK (0x300U) 967 #define DDRC_TIMING_CFG_4_EXT_WWT_SHIFT (8U) 968 #define DDRC_TIMING_CFG_4_EXT_WWT_WIDTH (2U) 969 #define DDRC_TIMING_CFG_4_EXT_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WWT_MASK) 970 971 #define DDRC_TIMING_CFG_4_EXT_RRT_MASK (0xC00U) 972 #define DDRC_TIMING_CFG_4_EXT_RRT_SHIFT (10U) 973 #define DDRC_TIMING_CFG_4_EXT_RRT_WIDTH (2U) 974 #define DDRC_TIMING_CFG_4_EXT_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RRT_MASK) 975 976 #define DDRC_TIMING_CFG_4_EXT_WRT_MASK (0x3000U) 977 #define DDRC_TIMING_CFG_4_EXT_WRT_SHIFT (12U) 978 #define DDRC_TIMING_CFG_4_EXT_WRT_WIDTH (2U) 979 #define DDRC_TIMING_CFG_4_EXT_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_WRT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_WRT_MASK) 980 981 #define DDRC_TIMING_CFG_4_EXT_RWT_MASK (0xC000U) 982 #define DDRC_TIMING_CFG_4_EXT_RWT_SHIFT (14U) 983 #define DDRC_TIMING_CFG_4_EXT_RWT_WIDTH (2U) 984 #define DDRC_TIMING_CFG_4_EXT_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_EXT_RWT_SHIFT)) & DDRC_TIMING_CFG_4_EXT_RWT_MASK) 985 986 #define DDRC_TIMING_CFG_4_WWT_MASK (0xF0000U) 987 #define DDRC_TIMING_CFG_4_WWT_SHIFT (16U) 988 #define DDRC_TIMING_CFG_4_WWT_WIDTH (4U) 989 #define DDRC_TIMING_CFG_4_WWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WWT_SHIFT)) & DDRC_TIMING_CFG_4_WWT_MASK) 990 991 #define DDRC_TIMING_CFG_4_RRT_MASK (0xF00000U) 992 #define DDRC_TIMING_CFG_4_RRT_SHIFT (20U) 993 #define DDRC_TIMING_CFG_4_RRT_WIDTH (4U) 994 #define DDRC_TIMING_CFG_4_RRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RRT_SHIFT)) & DDRC_TIMING_CFG_4_RRT_MASK) 995 996 #define DDRC_TIMING_CFG_4_WRT_MASK (0xF000000U) 997 #define DDRC_TIMING_CFG_4_WRT_SHIFT (24U) 998 #define DDRC_TIMING_CFG_4_WRT_WIDTH (4U) 999 #define DDRC_TIMING_CFG_4_WRT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_WRT_SHIFT)) & DDRC_TIMING_CFG_4_WRT_MASK) 1000 1001 #define DDRC_TIMING_CFG_4_RWT_MASK (0xF0000000U) 1002 #define DDRC_TIMING_CFG_4_RWT_SHIFT (28U) 1003 #define DDRC_TIMING_CFG_4_RWT_WIDTH (4U) 1004 #define DDRC_TIMING_CFG_4_RWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_4_RWT_SHIFT)) & DDRC_TIMING_CFG_4_RWT_MASK) 1005 /*! @} */ 1006 1007 /*! @name TIMING_CFG_7 - DDR SDRAM Timing Configuration 7 */ 1008 /*! @{ */ 1009 1010 #define DDRC_TIMING_CFG_7_CKSRX_MASK (0xF00000U) 1011 #define DDRC_TIMING_CFG_7_CKSRX_SHIFT (20U) 1012 #define DDRC_TIMING_CFG_7_CKSRX_WIDTH (4U) 1013 #define DDRC_TIMING_CFG_7_CKSRX(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRX_SHIFT)) & DDRC_TIMING_CFG_7_CKSRX_MASK) 1014 1015 #define DDRC_TIMING_CFG_7_CKSRE_MASK (0xF000000U) 1016 #define DDRC_TIMING_CFG_7_CKSRE_SHIFT (24U) 1017 #define DDRC_TIMING_CFG_7_CKSRE_WIDTH (4U) 1018 #define DDRC_TIMING_CFG_7_CKSRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKSRE_SHIFT)) & DDRC_TIMING_CFG_7_CKSRE_MASK) 1019 1020 #define DDRC_TIMING_CFG_7_CKE_RST_MASK (0x30000000U) 1021 #define DDRC_TIMING_CFG_7_CKE_RST_SHIFT (28U) 1022 #define DDRC_TIMING_CFG_7_CKE_RST_WIDTH (2U) 1023 #define DDRC_TIMING_CFG_7_CKE_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_7_CKE_RST_SHIFT)) & DDRC_TIMING_CFG_7_CKE_RST_MASK) 1024 /*! @} */ 1025 1026 /*! @name DDR_ZQ_CNTL - DDR SDRAM ZQ Calibration Control */ 1027 /*! @{ */ 1028 1029 #define DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK (0xFU) 1030 #define DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT (0U) 1031 #define DDRC_DDR_ZQ_CNTL_ZQCS_INT_WIDTH (4U) 1032 #define DDRC_DDR_ZQ_CNTL_ZQCS_INT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_INT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_INT_MASK) 1033 1034 #define DDRC_DDR_ZQ_CNTL_ZQCS_MASK (0xF00U) 1035 #define DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT (8U) 1036 #define DDRC_DDR_ZQ_CNTL_ZQCS_WIDTH (4U) 1037 #define DDRC_DDR_ZQ_CNTL_ZQCS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQCS_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQCS_MASK) 1038 1039 #define DDRC_DDR_ZQ_CNTL_ZQOPER_MASK (0xF0000U) 1040 #define DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT (16U) 1041 #define DDRC_DDR_ZQ_CNTL_ZQOPER_WIDTH (4U) 1042 #define DDRC_DDR_ZQ_CNTL_ZQOPER(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQOPER_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQOPER_MASK) 1043 1044 #define DDRC_DDR_ZQ_CNTL_ZQINIT_MASK (0xF000000U) 1045 #define DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT (24U) 1046 #define DDRC_DDR_ZQ_CNTL_ZQINIT_WIDTH (4U) 1047 #define DDRC_DDR_ZQ_CNTL_ZQINIT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQINIT_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQINIT_MASK) 1048 1049 #define DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK (0x80000000U) 1050 #define DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT (31U) 1051 #define DDRC_DDR_ZQ_CNTL_ZQ_EN_WIDTH (1U) 1052 #define DDRC_DDR_ZQ_CNTL_ZQ_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_ZQ_CNTL_ZQ_EN_SHIFT)) & DDRC_DDR_ZQ_CNTL_ZQ_EN_MASK) 1053 /*! @} */ 1054 1055 /*! @name DDR_SR_CNTR - DDR SDRAM Self-Refresh Counter */ 1056 /*! @{ */ 1057 1058 #define DDRC_DDR_SR_CNTR_SR_IT_MASK (0xF0000U) 1059 #define DDRC_DDR_SR_CNTR_SR_IT_SHIFT (16U) 1060 #define DDRC_DDR_SR_CNTR_SR_IT_WIDTH (4U) 1061 #define DDRC_DDR_SR_CNTR_SR_IT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SR_CNTR_SR_IT_SHIFT)) & DDRC_DDR_SR_CNTR_SR_IT_MASK) 1062 /*! @} */ 1063 1064 /*! @name TIMING_CFG_8 - DDR SDRAM Timing Configuration 8 */ 1065 /*! @{ */ 1066 1067 #define DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK (0x3FU) 1068 #define DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT (0U) 1069 #define DDRC_TIMING_CFG_8_PRE_ALL_REC_WIDTH (6U) 1070 #define DDRC_TIMING_CFG_8_PRE_ALL_REC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_8_PRE_ALL_REC_SHIFT)) & DDRC_TIMING_CFG_8_PRE_ALL_REC_MASK) 1071 /*! @} */ 1072 1073 /*! @name TIMING_CFG_9 - DDR SDRAM timing configuration 9 */ 1074 /*! @{ */ 1075 1076 #define DDRC_TIMING_CFG_9_REFTOREF_PB_MASK (0x3FFU) 1077 #define DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT (0U) 1078 #define DDRC_TIMING_CFG_9_REFTOREF_PB_WIDTH (10U) 1079 #define DDRC_TIMING_CFG_9_REFTOREF_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFTOREF_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFTOREF_PB_MASK) 1080 1081 #define DDRC_TIMING_CFG_9_REFREC_PB_MASK (0x3FF0000U) 1082 #define DDRC_TIMING_CFG_9_REFREC_PB_SHIFT (16U) 1083 #define DDRC_TIMING_CFG_9_REFREC_PB_WIDTH (10U) 1084 #define DDRC_TIMING_CFG_9_REFREC_PB(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_9_REFREC_PB_SHIFT)) & DDRC_TIMING_CFG_9_REFREC_PB_MASK) 1085 /*! @} */ 1086 1087 /*! @name TIMING_CFG_11 - DDR SDRAM Timing Configuration 11 */ 1088 /*! @{ */ 1089 1090 #define DDRC_TIMING_CFG_11_MWWT_MASK (0xFU) 1091 #define DDRC_TIMING_CFG_11_MWWT_SHIFT (0U) 1092 #define DDRC_TIMING_CFG_11_MWWT_WIDTH (4U) 1093 #define DDRC_TIMING_CFG_11_MWWT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_MWWT_SHIFT)) & DDRC_TIMING_CFG_11_MWWT_MASK) 1094 1095 #define DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK (0xF00U) 1096 #define DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT (8U) 1097 #define DDRC_TIMING_CFG_11_PRE_TO_PRE_WIDTH (4U) 1098 #define DDRC_TIMING_CFG_11_PRE_TO_PRE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TIMING_CFG_11_PRE_TO_PRE_SHIFT)) & DDRC_TIMING_CFG_11_PRE_TO_PRE_MASK) 1099 /*! @} */ 1100 1101 /*! @name DDR_SDRAM_CFG_3 - DDR SDRAM Control Configuration 3 */ 1102 /*! @{ */ 1103 1104 #define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK (0x2U) 1105 #define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT (1U) 1106 #define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_WIDTH (1U) 1107 #define DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_SR_FAST_WK_EN_MASK) 1108 1109 #define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK (0x8U) 1110 #define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT (3U) 1111 #define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_WIDTH (1U) 1112 #define DDRC_DDR_SDRAM_CFG_3_NON_PWR_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_NON_PWR_2_MASK) 1113 1114 #define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK (0x80U) 1115 #define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT (7U) 1116 #define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_WIDTH (1U) 1117 #define DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DYN_REF_RATE_EN_MASK) 1118 1119 #define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK (0x800U) 1120 #define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT (11U) 1121 #define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_WIDTH (1U) 1122 #define DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DRAIN_FOR_SR_MASK) 1123 1124 #define DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK (0x7000U) 1125 #define DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT (12U) 1126 #define DDRC_DDR_SDRAM_CFG_3_DM_CFG_WIDTH (3U) 1127 #define DDRC_DDR_SDRAM_CFG_3_DM_CFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DM_CFG_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DM_CFG_MASK) 1128 1129 #define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK (0x80000000U) 1130 #define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT (31U) 1131 #define DDRC_DDR_SDRAM_CFG_3_DDRC_RST_WIDTH (1U) 1132 #define DDRC_DDR_SDRAM_CFG_3_DDRC_RST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_CFG_3_DDRC_RST_SHIFT)) & DDRC_DDR_SDRAM_CFG_3_DDRC_RST_MASK) 1133 /*! @} */ 1134 1135 /*! @name DDR_SDRAM_REF_RATE - DDR Refresh Rate */ 1136 /*! @{ */ 1137 1138 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK (0xFFU) 1139 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT (0U) 1140 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_WIDTH (8U) 1141 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS1_MASK) 1142 1143 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK (0xFF00U) 1144 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT (8U) 1145 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_WIDTH (8U) 1146 #define DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_SHIFT)) & DDRC_DDR_SDRAM_REF_RATE_REF_RATE_CS0_MASK) 1147 /*! @} */ 1148 1149 /*! @name TX_CFG_1 - Transaction Configuration Register 1 */ 1150 /*! @{ */ 1151 1152 #define DDRC_TX_CFG_1_TS_DEPTH_MASK (0xF80U) 1153 #define DDRC_TX_CFG_1_TS_DEPTH_SHIFT (7U) 1154 #define DDRC_TX_CFG_1_TS_DEPTH_WIDTH (5U) 1155 #define DDRC_TX_CFG_1_TS_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_TX_CFG_1_TS_DEPTH_SHIFT)) & DDRC_TX_CFG_1_TS_DEPTH_MASK) 1156 /*! @} */ 1157 1158 /*! @name FFI_CFG - Freedom From Interference Configuration */ 1159 /*! @{ */ 1160 1161 #define DDRC_FFI_CFG_GRP_3_DID_MASK (0xFU) 1162 #define DDRC_FFI_CFG_GRP_3_DID_SHIFT (0U) 1163 #define DDRC_FFI_CFG_GRP_3_DID_WIDTH (4U) 1164 #define DDRC_FFI_CFG_GRP_3_DID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_3_DID_SHIFT)) & DDRC_FFI_CFG_GRP_3_DID_MASK) 1165 1166 #define DDRC_FFI_CFG_BNS_CNT_EN_MASK (0x10U) 1167 #define DDRC_FFI_CFG_BNS_CNT_EN_SHIFT (4U) 1168 #define DDRC_FFI_CFG_BNS_CNT_EN_WIDTH (1U) 1169 #define DDRC_FFI_CFG_BNS_CNT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_BNS_CNT_EN_SHIFT)) & DDRC_FFI_CFG_BNS_CNT_EN_MASK) 1170 1171 #define DDRC_FFI_CFG_GRP_DEF_EN_MASK (0x20U) 1172 #define DDRC_FFI_CFG_GRP_DEF_EN_SHIFT (5U) 1173 #define DDRC_FFI_CFG_GRP_DEF_EN_WIDTH (1U) 1174 #define DDRC_FFI_CFG_GRP_DEF_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_DEF_EN_SHIFT)) & DDRC_FFI_CFG_GRP_DEF_EN_MASK) 1175 1176 #define DDRC_FFI_CFG_GRP_3_AEN_MASK (0x40U) 1177 #define DDRC_FFI_CFG_GRP_3_AEN_SHIFT (6U) 1178 #define DDRC_FFI_CFG_GRP_3_AEN_WIDTH (1U) 1179 #define DDRC_FFI_CFG_GRP_3_AEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_3_AEN_SHIFT)) & DDRC_FFI_CFG_GRP_3_AEN_MASK) 1180 1181 #define DDRC_FFI_CFG_GRP_3_EN_MASK (0x80U) 1182 #define DDRC_FFI_CFG_GRP_3_EN_SHIFT (7U) 1183 #define DDRC_FFI_CFG_GRP_3_EN_WIDTH (1U) 1184 #define DDRC_FFI_CFG_GRP_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_3_EN_SHIFT)) & DDRC_FFI_CFG_GRP_3_EN_MASK) 1185 1186 #define DDRC_FFI_CFG_GRP_2_DID_MASK (0xF00U) 1187 #define DDRC_FFI_CFG_GRP_2_DID_SHIFT (8U) 1188 #define DDRC_FFI_CFG_GRP_2_DID_WIDTH (4U) 1189 #define DDRC_FFI_CFG_GRP_2_DID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_2_DID_SHIFT)) & DDRC_FFI_CFG_GRP_2_DID_MASK) 1190 1191 #define DDRC_FFI_CFG_GRP_2_EN_MASK (0x8000U) 1192 #define DDRC_FFI_CFG_GRP_2_EN_SHIFT (15U) 1193 #define DDRC_FFI_CFG_GRP_2_EN_WIDTH (1U) 1194 #define DDRC_FFI_CFG_GRP_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_2_EN_SHIFT)) & DDRC_FFI_CFG_GRP_2_EN_MASK) 1195 1196 #define DDRC_FFI_CFG_GRP_1_DID_MASK (0xF0000U) 1197 #define DDRC_FFI_CFG_GRP_1_DID_SHIFT (16U) 1198 #define DDRC_FFI_CFG_GRP_1_DID_WIDTH (4U) 1199 #define DDRC_FFI_CFG_GRP_1_DID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_1_DID_SHIFT)) & DDRC_FFI_CFG_GRP_1_DID_MASK) 1200 1201 #define DDRC_FFI_CFG_GRP_1_EN_MASK (0x800000U) 1202 #define DDRC_FFI_CFG_GRP_1_EN_SHIFT (23U) 1203 #define DDRC_FFI_CFG_GRP_1_EN_WIDTH (1U) 1204 #define DDRC_FFI_CFG_GRP_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_1_EN_SHIFT)) & DDRC_FFI_CFG_GRP_1_EN_MASK) 1205 1206 #define DDRC_FFI_CFG_GRP_0_DID_MASK (0xF000000U) 1207 #define DDRC_FFI_CFG_GRP_0_DID_SHIFT (24U) 1208 #define DDRC_FFI_CFG_GRP_0_DID_WIDTH (4U) 1209 #define DDRC_FFI_CFG_GRP_0_DID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_0_DID_SHIFT)) & DDRC_FFI_CFG_GRP_0_DID_MASK) 1210 1211 #define DDRC_FFI_CFG_GRP_0_EN_MASK (0x80000000U) 1212 #define DDRC_FFI_CFG_GRP_0_EN_SHIFT (31U) 1213 #define DDRC_FFI_CFG_GRP_0_EN_WIDTH (1U) 1214 #define DDRC_FFI_CFG_GRP_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG_GRP_0_EN_SHIFT)) & DDRC_FFI_CFG_GRP_0_EN_MASK) 1215 /*! @} */ 1216 1217 /*! @name FFI_CFG2 - Freedom From Interference Configuration 2 */ 1218 /*! @{ */ 1219 1220 #define DDRC_FFI_CFG2_INF_DEF_BNS_MASK (0x1U) 1221 #define DDRC_FFI_CFG2_INF_DEF_BNS_SHIFT (0U) 1222 #define DDRC_FFI_CFG2_INF_DEF_BNS_WIDTH (1U) 1223 #define DDRC_FFI_CFG2_INF_DEF_BNS(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG2_INF_DEF_BNS_SHIFT)) & DDRC_FFI_CFG2_INF_DEF_BNS_MASK) 1224 1225 #define DDRC_FFI_CFG2_BNS_CNT_CNFG_MASK (0x1F0U) 1226 #define DDRC_FFI_CFG2_BNS_CNT_CNFG_SHIFT (4U) 1227 #define DDRC_FFI_CFG2_BNS_CNT_CNFG_WIDTH (5U) 1228 #define DDRC_FFI_CFG2_BNS_CNT_CNFG(x) (((uint32_t)(((uint32_t)(x)) << DDRC_FFI_CFG2_BNS_CNT_CNFG_SHIFT)) & DDRC_FFI_CFG2_BNS_CNT_CNFG_MASK) 1229 /*! @} */ 1230 1231 /*! @name DDRDSR_2 - DDR SDRAM Debug Status 2 */ 1232 /*! @{ */ 1233 1234 #define DDRC_DDRDSR_2_RPD_END_MASK (0x1U) 1235 #define DDRC_DDRDSR_2_RPD_END_SHIFT (0U) 1236 #define DDRC_DDRDSR_2_RPD_END_WIDTH (1U) 1237 #define DDRC_DDRDSR_2_RPD_END(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_END_SHIFT)) & DDRC_DDRDSR_2_RPD_END_MASK) 1238 1239 #define DDRC_DDRDSR_2_RPD_ST_MASK (0x2U) 1240 #define DDRC_DDRDSR_2_RPD_ST_SHIFT (1U) 1241 #define DDRC_DDRDSR_2_RPD_ST_WIDTH (1U) 1242 #define DDRC_DDRDSR_2_RPD_ST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_RPD_ST_SHIFT)) & DDRC_DDRDSR_2_RPD_ST_MASK) 1243 1244 #define DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK (0x4U) 1245 #define DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT (2U) 1246 #define DDRC_DDRDSR_2_PHY_INIT_CMPLT_WIDTH (1U) 1247 #define DDRC_DDRDSR_2_PHY_INIT_CMPLT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_PHY_INIT_CMPLT_SHIFT)) & DDRC_DDRDSR_2_PHY_INIT_CMPLT_MASK) 1248 1249 #define DDRC_DDRDSR_2_NML_MASK (0x40000000U) 1250 #define DDRC_DDRDSR_2_NML_SHIFT (30U) 1251 #define DDRC_DDRDSR_2_NML_WIDTH (1U) 1252 #define DDRC_DDRDSR_2_NML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_NML_SHIFT)) & DDRC_DDRDSR_2_NML_MASK) 1253 1254 #define DDRC_DDRDSR_2_IDLE_MASK (0x80000000U) 1255 #define DDRC_DDRDSR_2_IDLE_SHIFT (31U) 1256 #define DDRC_DDRDSR_2_IDLE_WIDTH (1U) 1257 #define DDRC_DDRDSR_2_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDRDSR_2_IDLE_SHIFT)) & DDRC_DDRDSR_2_IDLE_MASK) 1258 /*! @} */ 1259 1260 /*! @name DDR_IP_REV1 - DDRC Revision 1 */ 1261 /*! @{ */ 1262 1263 #define DDRC_DDR_IP_REV1_IP_MN_MASK (0xFFU) 1264 #define DDRC_DDR_IP_REV1_IP_MN_SHIFT (0U) 1265 #define DDRC_DDR_IP_REV1_IP_MN_WIDTH (8U) 1266 #define DDRC_DDR_IP_REV1_IP_MN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MN_SHIFT)) & DDRC_DDR_IP_REV1_IP_MN_MASK) 1267 1268 #define DDRC_DDR_IP_REV1_IP_MJ_MASK (0xFF00U) 1269 #define DDRC_DDR_IP_REV1_IP_MJ_SHIFT (8U) 1270 #define DDRC_DDR_IP_REV1_IP_MJ_WIDTH (8U) 1271 #define DDRC_DDR_IP_REV1_IP_MJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_MJ_SHIFT)) & DDRC_DDR_IP_REV1_IP_MJ_MASK) 1272 1273 #define DDRC_DDR_IP_REV1_IP_ID_MASK (0xFFFF0000U) 1274 #define DDRC_DDR_IP_REV1_IP_ID_SHIFT (16U) 1275 #define DDRC_DDR_IP_REV1_IP_ID_WIDTH (16U) 1276 #define DDRC_DDR_IP_REV1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_IP_REV1_IP_ID_SHIFT)) & DDRC_DDR_IP_REV1_IP_ID_MASK) 1277 /*! @} */ 1278 1279 /*! @name DDR_MTCR - DDR SDRAM Memory Test Control */ 1280 /*! @{ */ 1281 1282 #define DDRC_DDR_MTCR_MT_STAT_MASK (0x1U) 1283 #define DDRC_DDR_MTCR_MT_STAT_SHIFT (0U) 1284 #define DDRC_DDR_MTCR_MT_STAT_WIDTH (1U) 1285 #define DDRC_DDR_MTCR_MT_STAT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_STAT_SHIFT)) & DDRC_DDR_MTCR_MT_STAT_MASK) 1286 1287 #define DDRC_DDR_MTCR_MT_ADDR_EN_MASK (0x200U) 1288 #define DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT (9U) 1289 #define DDRC_DDR_MTCR_MT_ADDR_EN_WIDTH (1U) 1290 #define DDRC_DDR_MTCR_MT_ADDR_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_ADDR_EN_SHIFT)) & DDRC_DDR_MTCR_MT_ADDR_EN_MASK) 1291 1292 #define DDRC_DDR_MTCR_MT_TRNARND_MASK (0xF0000U) 1293 #define DDRC_DDR_MTCR_MT_TRNARND_SHIFT (16U) 1294 #define DDRC_DDR_MTCR_MT_TRNARND_WIDTH (4U) 1295 #define DDRC_DDR_MTCR_MT_TRNARND(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TRNARND_SHIFT)) & DDRC_DDR_MTCR_MT_TRNARND_MASK) 1296 1297 #define DDRC_DDR_MTCR_MT_TYP_MASK (0x3000000U) 1298 #define DDRC_DDR_MTCR_MT_TYP_SHIFT (24U) 1299 #define DDRC_DDR_MTCR_MT_TYP_WIDTH (2U) 1300 #define DDRC_DDR_MTCR_MT_TYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_TYP_SHIFT)) & DDRC_DDR_MTCR_MT_TYP_MASK) 1301 1302 #define DDRC_DDR_MTCR_MT_EN_MASK (0x80000000U) 1303 #define DDRC_DDR_MTCR_MT_EN_SHIFT (31U) 1304 #define DDRC_DDR_MTCR_MT_EN_WIDTH (1U) 1305 #define DDRC_DDR_MTCR_MT_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTCR_MT_EN_SHIFT)) & DDRC_DDR_MTCR_MT_EN_MASK) 1306 /*! @} */ 1307 1308 /*! @name DDR_MTP - DDR SDRAM Memory Test Pattern n */ 1309 /*! @{ */ 1310 1311 #define DDRC_DDR_MTP_DDR_PATT_MASK (0xFFFFFFFFU) 1312 #define DDRC_DDR_MTP_DDR_PATT_SHIFT (0U) 1313 #define DDRC_DDR_MTP_DDR_PATT_WIDTH (32U) 1314 #define DDRC_DDR_MTP_DDR_PATT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MTP_DDR_PATT_SHIFT)) & DDRC_DDR_MTP_DDR_PATT_MASK) 1315 /*! @} */ 1316 1317 /*! @name DDR_MT_ST_EXT_ADDR - DDR SDRAM Memory Test Start Extended Address */ 1318 /*! @{ */ 1319 1320 #define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK (0xFFU) 1321 #define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT (0U) 1322 #define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_WIDTH (8U) 1323 #define DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_ST_EXT_ADDR_MT_ST_EXT_ADDR_MASK) 1324 /*! @} */ 1325 1326 /*! @name DDR_MT_ST_ADDR - DDR SDRAM Memory Test Start Address */ 1327 /*! @{ */ 1328 1329 #define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK (0xFFFFFFFFU) 1330 #define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT (0U) 1331 #define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_WIDTH (32U) 1332 #define DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_SHIFT)) & DDRC_DDR_MT_ST_ADDR_MT_ST_ADDR_MASK) 1333 /*! @} */ 1334 1335 /*! @name DDR_MT_END_EXT_ADDR - DDR SDRAM Memory Test End Extended Address */ 1336 /*! @{ */ 1337 1338 #define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK (0xFFU) 1339 #define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT (0U) 1340 #define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_WIDTH (8U) 1341 #define DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_SHIFT)) & DDRC_DDR_MT_END_EXT_ADDR_MT_END_EXT_ADDR_MASK) 1342 /*! @} */ 1343 1344 /*! @name DDR_MT_END_ADDR - DDR SDRAM Memory Test End Address */ 1345 /*! @{ */ 1346 1347 #define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK (0xFFFFFFFFU) 1348 #define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT (0U) 1349 #define DDRC_DDR_MT_END_ADDR_MT_END_ADDR_WIDTH (32U) 1350 #define DDRC_DDR_MT_END_ADDR_MT_END_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DDR_MT_END_ADDR_MT_END_ADDR_SHIFT)) & DDRC_DDR_MT_END_ADDR_MT_END_ADDR_MASK) 1351 /*! @} */ 1352 1353 /*! @name PMGC0 - Performance Monitor Global Control */ 1354 /*! @{ */ 1355 1356 #define DDRC_PMGC0_FCECE_MASK (0x20000000U) 1357 #define DDRC_PMGC0_FCECE_SHIFT (29U) 1358 #define DDRC_PMGC0_FCECE_WIDTH (1U) 1359 #define DDRC_PMGC0_FCECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FCECE_SHIFT)) & DDRC_PMGC0_FCECE_MASK) 1360 1361 #define DDRC_PMGC0_PMIE_MASK (0x40000000U) 1362 #define DDRC_PMGC0_PMIE_SHIFT (30U) 1363 #define DDRC_PMGC0_PMIE_WIDTH (1U) 1364 #define DDRC_PMGC0_PMIE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_PMIE_SHIFT)) & DDRC_PMGC0_PMIE_MASK) 1365 1366 #define DDRC_PMGC0_FAC_MASK (0x80000000U) 1367 #define DDRC_PMGC0_FAC_SHIFT (31U) 1368 #define DDRC_PMGC0_FAC_WIDTH (1U) 1369 #define DDRC_PMGC0_FAC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMGC0_FAC_SHIFT)) & DDRC_PMGC0_FAC_MASK) 1370 /*! @} */ 1371 1372 /*! @name PMLCA0 - Performance Monitor Local Control A0 */ 1373 /*! @{ */ 1374 1375 #define DDRC_PMLCA0_CE_MASK (0x4000000U) 1376 #define DDRC_PMLCA0_CE_SHIFT (26U) 1377 #define DDRC_PMLCA0_CE_WIDTH (1U) 1378 #define DDRC_PMLCA0_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_CE_SHIFT)) & DDRC_PMLCA0_CE_MASK) 1379 1380 #define DDRC_PMLCA0_FC_MASK (0x80000000U) 1381 #define DDRC_PMLCA0_FC_SHIFT (31U) 1382 #define DDRC_PMLCA0_FC_WIDTH (1U) 1383 #define DDRC_PMLCA0_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA0_FC_SHIFT)) & DDRC_PMLCA0_FC_MASK) 1384 /*! @} */ 1385 1386 /*! @name PMLCB0 - Performance Monitor Local Control B0 */ 1387 /*! @{ */ 1388 1389 #define DDRC_PMLCB0_TRIGOFFCNTL_MASK (0x30000U) 1390 #define DDRC_PMLCB0_TRIGOFFCNTL_SHIFT (16U) 1391 #define DDRC_PMLCB0_TRIGOFFCNTL_WIDTH (2U) 1392 #define DDRC_PMLCB0_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB0_TRIGOFFCNTL_MASK) 1393 1394 #define DDRC_PMLCB0_TRIGONCNTL_MASK (0xC0000U) 1395 #define DDRC_PMLCB0_TRIGONCNTL_SHIFT (18U) 1396 #define DDRC_PMLCB0_TRIGONCNTL_WIDTH (2U) 1397 #define DDRC_PMLCB0_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONCNTL_SHIFT)) & DDRC_PMLCB0_TRIGONCNTL_MASK) 1398 1399 #define DDRC_PMLCB0_TRIGOFFSEL_MASK (0xF00000U) 1400 #define DDRC_PMLCB0_TRIGOFFSEL_SHIFT (20U) 1401 #define DDRC_PMLCB0_TRIGOFFSEL_WIDTH (4U) 1402 #define DDRC_PMLCB0_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB0_TRIGOFFSEL_MASK) 1403 1404 #define DDRC_PMLCB0_TRIGONSEL_MASK (0x3C000000U) 1405 #define DDRC_PMLCB0_TRIGONSEL_SHIFT (26U) 1406 #define DDRC_PMLCB0_TRIGONSEL_WIDTH (4U) 1407 #define DDRC_PMLCB0_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB0_TRIGONSEL_SHIFT)) & DDRC_PMLCB0_TRIGONSEL_MASK) 1408 /*! @} */ 1409 1410 /*! @name PMC0A - PMC 0a */ 1411 /*! @{ */ 1412 1413 #define DDRC_PMC0A_PMC0_MASK (0xFFFFFFFFU) 1414 #define DDRC_PMC0A_PMC0_SHIFT (0U) 1415 #define DDRC_PMC0A_PMC0_WIDTH (32U) 1416 #define DDRC_PMC0A_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0A_PMC0_SHIFT)) & DDRC_PMC0A_PMC0_MASK) 1417 /*! @} */ 1418 1419 /*! @name PMC0B - PMC 0b */ 1420 /*! @{ */ 1421 1422 #define DDRC_PMC0B_PMC0_MASK (0xFFFFFFFFU) 1423 #define DDRC_PMC0B_PMC0_SHIFT (0U) 1424 #define DDRC_PMC0B_PMC0_WIDTH (32U) 1425 #define DDRC_PMC0B_PMC0(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC0B_PMC0_SHIFT)) & DDRC_PMC0B_PMC0_MASK) 1426 /*! @} */ 1427 1428 /*! @name PMLCA1 - Performance Monitor Local Control A */ 1429 /*! @{ */ 1430 1431 #define DDRC_PMLCA1_BDIST_MASK (0x3FU) 1432 #define DDRC_PMLCA1_BDIST_SHIFT (0U) 1433 #define DDRC_PMLCA1_BDIST_WIDTH (6U) 1434 #define DDRC_PMLCA1_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BDIST_SHIFT)) & DDRC_PMLCA1_BDIST_MASK) 1435 1436 #define DDRC_PMLCA1_BGRAN_MASK (0x7C0U) 1437 #define DDRC_PMLCA1_BGRAN_SHIFT (6U) 1438 #define DDRC_PMLCA1_BGRAN_WIDTH (5U) 1439 #define DDRC_PMLCA1_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BGRAN_SHIFT)) & DDRC_PMLCA1_BGRAN_MASK) 1440 1441 #define DDRC_PMLCA1_BSIZE_MASK (0xF800U) 1442 #define DDRC_PMLCA1_BSIZE_SHIFT (11U) 1443 #define DDRC_PMLCA1_BSIZE_WIDTH (5U) 1444 #define DDRC_PMLCA1_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_BSIZE_SHIFT)) & DDRC_PMLCA1_BSIZE_MASK) 1445 1446 #define DDRC_PMLCA1_EVENT_MASK (0x7F0000U) 1447 #define DDRC_PMLCA1_EVENT_SHIFT (16U) 1448 #define DDRC_PMLCA1_EVENT_WIDTH (7U) 1449 #define DDRC_PMLCA1_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_EVENT_SHIFT)) & DDRC_PMLCA1_EVENT_MASK) 1450 1451 #define DDRC_PMLCA1_CE_MASK (0x4000000U) 1452 #define DDRC_PMLCA1_CE_SHIFT (26U) 1453 #define DDRC_PMLCA1_CE_WIDTH (1U) 1454 #define DDRC_PMLCA1_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_CE_SHIFT)) & DDRC_PMLCA1_CE_MASK) 1455 1456 #define DDRC_PMLCA1_FC_MASK (0x80000000U) 1457 #define DDRC_PMLCA1_FC_SHIFT (31U) 1458 #define DDRC_PMLCA1_FC_WIDTH (1U) 1459 #define DDRC_PMLCA1_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA1_FC_SHIFT)) & DDRC_PMLCA1_FC_MASK) 1460 /*! @} */ 1461 1462 /*! @name PMLCB1 - Performance Monitor Local Control B */ 1463 /*! @{ */ 1464 1465 #define DDRC_PMLCB1_THRESHOLD_MASK (0x3FU) 1466 #define DDRC_PMLCB1_THRESHOLD_SHIFT (0U) 1467 #define DDRC_PMLCB1_THRESHOLD_WIDTH (6U) 1468 #define DDRC_PMLCB1_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_THRESHOLD_SHIFT)) & DDRC_PMLCB1_THRESHOLD_MASK) 1469 1470 #define DDRC_PMLCB1_TBMULT_MASK (0x700U) 1471 #define DDRC_PMLCB1_TBMULT_SHIFT (8U) 1472 #define DDRC_PMLCB1_TBMULT_WIDTH (3U) 1473 #define DDRC_PMLCB1_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TBMULT_SHIFT)) & DDRC_PMLCB1_TBMULT_MASK) 1474 1475 #define DDRC_PMLCB1_TRIGOFFCNTL_MASK (0x30000U) 1476 #define DDRC_PMLCB1_TRIGOFFCNTL_SHIFT (16U) 1477 #define DDRC_PMLCB1_TRIGOFFCNTL_WIDTH (2U) 1478 #define DDRC_PMLCB1_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB1_TRIGOFFCNTL_MASK) 1479 1480 #define DDRC_PMLCB1_TRIGONCNTL_MASK (0xC0000U) 1481 #define DDRC_PMLCB1_TRIGONCNTL_SHIFT (18U) 1482 #define DDRC_PMLCB1_TRIGONCNTL_WIDTH (2U) 1483 #define DDRC_PMLCB1_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONCNTL_SHIFT)) & DDRC_PMLCB1_TRIGONCNTL_MASK) 1484 1485 #define DDRC_PMLCB1_TRIGOFFSEL_MASK (0xF00000U) 1486 #define DDRC_PMLCB1_TRIGOFFSEL_SHIFT (20U) 1487 #define DDRC_PMLCB1_TRIGOFFSEL_WIDTH (4U) 1488 #define DDRC_PMLCB1_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB1_TRIGOFFSEL_MASK) 1489 1490 #define DDRC_PMLCB1_TRIGONSEL_MASK (0x3C000000U) 1491 #define DDRC_PMLCB1_TRIGONSEL_SHIFT (26U) 1492 #define DDRC_PMLCB1_TRIGONSEL_WIDTH (4U) 1493 #define DDRC_PMLCB1_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB1_TRIGONSEL_SHIFT)) & DDRC_PMLCB1_TRIGONSEL_MASK) 1494 /*! @} */ 1495 1496 /*! @name PMC1 - Performance Monitor Counter */ 1497 /*! @{ */ 1498 1499 #define DDRC_PMC1_PMC1_MASK (0xFFFFFFFFU) 1500 #define DDRC_PMC1_PMC1_SHIFT (0U) 1501 #define DDRC_PMC1_PMC1_WIDTH (32U) 1502 #define DDRC_PMC1_PMC1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC1_PMC1_SHIFT)) & DDRC_PMC1_PMC1_MASK) 1503 /*! @} */ 1504 1505 /*! @name PMLCA2 - Performance Monitor Local Control A */ 1506 /*! @{ */ 1507 1508 #define DDRC_PMLCA2_BDIST_MASK (0x3FU) 1509 #define DDRC_PMLCA2_BDIST_SHIFT (0U) 1510 #define DDRC_PMLCA2_BDIST_WIDTH (6U) 1511 #define DDRC_PMLCA2_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BDIST_SHIFT)) & DDRC_PMLCA2_BDIST_MASK) 1512 1513 #define DDRC_PMLCA2_BGRAN_MASK (0x7C0U) 1514 #define DDRC_PMLCA2_BGRAN_SHIFT (6U) 1515 #define DDRC_PMLCA2_BGRAN_WIDTH (5U) 1516 #define DDRC_PMLCA2_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BGRAN_SHIFT)) & DDRC_PMLCA2_BGRAN_MASK) 1517 1518 #define DDRC_PMLCA2_BSIZE_MASK (0xF800U) 1519 #define DDRC_PMLCA2_BSIZE_SHIFT (11U) 1520 #define DDRC_PMLCA2_BSIZE_WIDTH (5U) 1521 #define DDRC_PMLCA2_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_BSIZE_SHIFT)) & DDRC_PMLCA2_BSIZE_MASK) 1522 1523 #define DDRC_PMLCA2_EVENT_MASK (0x7F0000U) 1524 #define DDRC_PMLCA2_EVENT_SHIFT (16U) 1525 #define DDRC_PMLCA2_EVENT_WIDTH (7U) 1526 #define DDRC_PMLCA2_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_EVENT_SHIFT)) & DDRC_PMLCA2_EVENT_MASK) 1527 1528 #define DDRC_PMLCA2_CE_MASK (0x4000000U) 1529 #define DDRC_PMLCA2_CE_SHIFT (26U) 1530 #define DDRC_PMLCA2_CE_WIDTH (1U) 1531 #define DDRC_PMLCA2_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_CE_SHIFT)) & DDRC_PMLCA2_CE_MASK) 1532 1533 #define DDRC_PMLCA2_FC_MASK (0x80000000U) 1534 #define DDRC_PMLCA2_FC_SHIFT (31U) 1535 #define DDRC_PMLCA2_FC_WIDTH (1U) 1536 #define DDRC_PMLCA2_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA2_FC_SHIFT)) & DDRC_PMLCA2_FC_MASK) 1537 /*! @} */ 1538 1539 /*! @name PMLCB2 - Performance Monitor Local Control B */ 1540 /*! @{ */ 1541 1542 #define DDRC_PMLCB2_THRESHOLD_MASK (0x3FU) 1543 #define DDRC_PMLCB2_THRESHOLD_SHIFT (0U) 1544 #define DDRC_PMLCB2_THRESHOLD_WIDTH (6U) 1545 #define DDRC_PMLCB2_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_THRESHOLD_SHIFT)) & DDRC_PMLCB2_THRESHOLD_MASK) 1546 1547 #define DDRC_PMLCB2_TBMULT_MASK (0x700U) 1548 #define DDRC_PMLCB2_TBMULT_SHIFT (8U) 1549 #define DDRC_PMLCB2_TBMULT_WIDTH (3U) 1550 #define DDRC_PMLCB2_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TBMULT_SHIFT)) & DDRC_PMLCB2_TBMULT_MASK) 1551 1552 #define DDRC_PMLCB2_TRIGOFFCNTL_MASK (0x30000U) 1553 #define DDRC_PMLCB2_TRIGOFFCNTL_SHIFT (16U) 1554 #define DDRC_PMLCB2_TRIGOFFCNTL_WIDTH (2U) 1555 #define DDRC_PMLCB2_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB2_TRIGOFFCNTL_MASK) 1556 1557 #define DDRC_PMLCB2_TRIGONCNTL_MASK (0xC0000U) 1558 #define DDRC_PMLCB2_TRIGONCNTL_SHIFT (18U) 1559 #define DDRC_PMLCB2_TRIGONCNTL_WIDTH (2U) 1560 #define DDRC_PMLCB2_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONCNTL_SHIFT)) & DDRC_PMLCB2_TRIGONCNTL_MASK) 1561 1562 #define DDRC_PMLCB2_TRIGOFFSEL_MASK (0xF00000U) 1563 #define DDRC_PMLCB2_TRIGOFFSEL_SHIFT (20U) 1564 #define DDRC_PMLCB2_TRIGOFFSEL_WIDTH (4U) 1565 #define DDRC_PMLCB2_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB2_TRIGOFFSEL_MASK) 1566 1567 #define DDRC_PMLCB2_TRIGONSEL_MASK (0x3C000000U) 1568 #define DDRC_PMLCB2_TRIGONSEL_SHIFT (26U) 1569 #define DDRC_PMLCB2_TRIGONSEL_WIDTH (4U) 1570 #define DDRC_PMLCB2_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB2_TRIGONSEL_SHIFT)) & DDRC_PMLCB2_TRIGONSEL_MASK) 1571 /*! @} */ 1572 1573 /*! @name PMC2 - Performance Monitor Counter */ 1574 /*! @{ */ 1575 1576 #define DDRC_PMC2_PMC2_MASK (0xFFFFFFFFU) 1577 #define DDRC_PMC2_PMC2_SHIFT (0U) 1578 #define DDRC_PMC2_PMC2_WIDTH (32U) 1579 #define DDRC_PMC2_PMC2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC2_PMC2_SHIFT)) & DDRC_PMC2_PMC2_MASK) 1580 /*! @} */ 1581 1582 /*! @name PMLCA3 - Performance Monitor Local Control A */ 1583 /*! @{ */ 1584 1585 #define DDRC_PMLCA3_BDIST_MASK (0x3FU) 1586 #define DDRC_PMLCA3_BDIST_SHIFT (0U) 1587 #define DDRC_PMLCA3_BDIST_WIDTH (6U) 1588 #define DDRC_PMLCA3_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BDIST_SHIFT)) & DDRC_PMLCA3_BDIST_MASK) 1589 1590 #define DDRC_PMLCA3_BGRAN_MASK (0x7C0U) 1591 #define DDRC_PMLCA3_BGRAN_SHIFT (6U) 1592 #define DDRC_PMLCA3_BGRAN_WIDTH (5U) 1593 #define DDRC_PMLCA3_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BGRAN_SHIFT)) & DDRC_PMLCA3_BGRAN_MASK) 1594 1595 #define DDRC_PMLCA3_BSIZE_MASK (0xF800U) 1596 #define DDRC_PMLCA3_BSIZE_SHIFT (11U) 1597 #define DDRC_PMLCA3_BSIZE_WIDTH (5U) 1598 #define DDRC_PMLCA3_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_BSIZE_SHIFT)) & DDRC_PMLCA3_BSIZE_MASK) 1599 1600 #define DDRC_PMLCA3_EVENT_MASK (0x7F0000U) 1601 #define DDRC_PMLCA3_EVENT_SHIFT (16U) 1602 #define DDRC_PMLCA3_EVENT_WIDTH (7U) 1603 #define DDRC_PMLCA3_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_EVENT_SHIFT)) & DDRC_PMLCA3_EVENT_MASK) 1604 1605 #define DDRC_PMLCA3_CE_MASK (0x4000000U) 1606 #define DDRC_PMLCA3_CE_SHIFT (26U) 1607 #define DDRC_PMLCA3_CE_WIDTH (1U) 1608 #define DDRC_PMLCA3_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_CE_SHIFT)) & DDRC_PMLCA3_CE_MASK) 1609 1610 #define DDRC_PMLCA3_FC_MASK (0x80000000U) 1611 #define DDRC_PMLCA3_FC_SHIFT (31U) 1612 #define DDRC_PMLCA3_FC_WIDTH (1U) 1613 #define DDRC_PMLCA3_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA3_FC_SHIFT)) & DDRC_PMLCA3_FC_MASK) 1614 /*! @} */ 1615 1616 /*! @name PMLCB3 - Performance Monitor Local Control B */ 1617 /*! @{ */ 1618 1619 #define DDRC_PMLCB3_THRESHOLD_MASK (0x3FU) 1620 #define DDRC_PMLCB3_THRESHOLD_SHIFT (0U) 1621 #define DDRC_PMLCB3_THRESHOLD_WIDTH (6U) 1622 #define DDRC_PMLCB3_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_THRESHOLD_SHIFT)) & DDRC_PMLCB3_THRESHOLD_MASK) 1623 1624 #define DDRC_PMLCB3_TBMULT_MASK (0x700U) 1625 #define DDRC_PMLCB3_TBMULT_SHIFT (8U) 1626 #define DDRC_PMLCB3_TBMULT_WIDTH (3U) 1627 #define DDRC_PMLCB3_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TBMULT_SHIFT)) & DDRC_PMLCB3_TBMULT_MASK) 1628 1629 #define DDRC_PMLCB3_TRIGOFFCNTL_MASK (0x30000U) 1630 #define DDRC_PMLCB3_TRIGOFFCNTL_SHIFT (16U) 1631 #define DDRC_PMLCB3_TRIGOFFCNTL_WIDTH (2U) 1632 #define DDRC_PMLCB3_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB3_TRIGOFFCNTL_MASK) 1633 1634 #define DDRC_PMLCB3_TRIGONCNTL_MASK (0xC0000U) 1635 #define DDRC_PMLCB3_TRIGONCNTL_SHIFT (18U) 1636 #define DDRC_PMLCB3_TRIGONCNTL_WIDTH (2U) 1637 #define DDRC_PMLCB3_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONCNTL_SHIFT)) & DDRC_PMLCB3_TRIGONCNTL_MASK) 1638 1639 #define DDRC_PMLCB3_TRIGOFFSEL_MASK (0xF00000U) 1640 #define DDRC_PMLCB3_TRIGOFFSEL_SHIFT (20U) 1641 #define DDRC_PMLCB3_TRIGOFFSEL_WIDTH (4U) 1642 #define DDRC_PMLCB3_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB3_TRIGOFFSEL_MASK) 1643 1644 #define DDRC_PMLCB3_TRIGONSEL_MASK (0x3C000000U) 1645 #define DDRC_PMLCB3_TRIGONSEL_SHIFT (26U) 1646 #define DDRC_PMLCB3_TRIGONSEL_WIDTH (4U) 1647 #define DDRC_PMLCB3_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB3_TRIGONSEL_SHIFT)) & DDRC_PMLCB3_TRIGONSEL_MASK) 1648 /*! @} */ 1649 1650 /*! @name PMC3 - Performance Monitor Counter */ 1651 /*! @{ */ 1652 1653 #define DDRC_PMC3_PMC3_MASK (0xFFFFFFFFU) 1654 #define DDRC_PMC3_PMC3_SHIFT (0U) 1655 #define DDRC_PMC3_PMC3_WIDTH (32U) 1656 #define DDRC_PMC3_PMC3(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC3_PMC3_SHIFT)) & DDRC_PMC3_PMC3_MASK) 1657 /*! @} */ 1658 1659 /*! @name PMLCA4 - Performance Monitor Local Control A */ 1660 /*! @{ */ 1661 1662 #define DDRC_PMLCA4_BDIST_MASK (0x3FU) 1663 #define DDRC_PMLCA4_BDIST_SHIFT (0U) 1664 #define DDRC_PMLCA4_BDIST_WIDTH (6U) 1665 #define DDRC_PMLCA4_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BDIST_SHIFT)) & DDRC_PMLCA4_BDIST_MASK) 1666 1667 #define DDRC_PMLCA4_BGRAN_MASK (0x7C0U) 1668 #define DDRC_PMLCA4_BGRAN_SHIFT (6U) 1669 #define DDRC_PMLCA4_BGRAN_WIDTH (5U) 1670 #define DDRC_PMLCA4_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BGRAN_SHIFT)) & DDRC_PMLCA4_BGRAN_MASK) 1671 1672 #define DDRC_PMLCA4_BSIZE_MASK (0xF800U) 1673 #define DDRC_PMLCA4_BSIZE_SHIFT (11U) 1674 #define DDRC_PMLCA4_BSIZE_WIDTH (5U) 1675 #define DDRC_PMLCA4_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_BSIZE_SHIFT)) & DDRC_PMLCA4_BSIZE_MASK) 1676 1677 #define DDRC_PMLCA4_EVENT_MASK (0x7F0000U) 1678 #define DDRC_PMLCA4_EVENT_SHIFT (16U) 1679 #define DDRC_PMLCA4_EVENT_WIDTH (7U) 1680 #define DDRC_PMLCA4_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_EVENT_SHIFT)) & DDRC_PMLCA4_EVENT_MASK) 1681 1682 #define DDRC_PMLCA4_CE_MASK (0x4000000U) 1683 #define DDRC_PMLCA4_CE_SHIFT (26U) 1684 #define DDRC_PMLCA4_CE_WIDTH (1U) 1685 #define DDRC_PMLCA4_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_CE_SHIFT)) & DDRC_PMLCA4_CE_MASK) 1686 1687 #define DDRC_PMLCA4_FC_MASK (0x80000000U) 1688 #define DDRC_PMLCA4_FC_SHIFT (31U) 1689 #define DDRC_PMLCA4_FC_WIDTH (1U) 1690 #define DDRC_PMLCA4_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA4_FC_SHIFT)) & DDRC_PMLCA4_FC_MASK) 1691 /*! @} */ 1692 1693 /*! @name PMLCB4 - Performance Monitor Local Control B */ 1694 /*! @{ */ 1695 1696 #define DDRC_PMLCB4_THRESHOLD_MASK (0x3FU) 1697 #define DDRC_PMLCB4_THRESHOLD_SHIFT (0U) 1698 #define DDRC_PMLCB4_THRESHOLD_WIDTH (6U) 1699 #define DDRC_PMLCB4_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_THRESHOLD_SHIFT)) & DDRC_PMLCB4_THRESHOLD_MASK) 1700 1701 #define DDRC_PMLCB4_TBMULT_MASK (0x700U) 1702 #define DDRC_PMLCB4_TBMULT_SHIFT (8U) 1703 #define DDRC_PMLCB4_TBMULT_WIDTH (3U) 1704 #define DDRC_PMLCB4_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TBMULT_SHIFT)) & DDRC_PMLCB4_TBMULT_MASK) 1705 1706 #define DDRC_PMLCB4_TRIGOFFCNTL_MASK (0x30000U) 1707 #define DDRC_PMLCB4_TRIGOFFCNTL_SHIFT (16U) 1708 #define DDRC_PMLCB4_TRIGOFFCNTL_WIDTH (2U) 1709 #define DDRC_PMLCB4_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB4_TRIGOFFCNTL_MASK) 1710 1711 #define DDRC_PMLCB4_TRIGONCNTL_MASK (0xC0000U) 1712 #define DDRC_PMLCB4_TRIGONCNTL_SHIFT (18U) 1713 #define DDRC_PMLCB4_TRIGONCNTL_WIDTH (2U) 1714 #define DDRC_PMLCB4_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONCNTL_SHIFT)) & DDRC_PMLCB4_TRIGONCNTL_MASK) 1715 1716 #define DDRC_PMLCB4_TRIGOFFSEL_MASK (0xF00000U) 1717 #define DDRC_PMLCB4_TRIGOFFSEL_SHIFT (20U) 1718 #define DDRC_PMLCB4_TRIGOFFSEL_WIDTH (4U) 1719 #define DDRC_PMLCB4_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB4_TRIGOFFSEL_MASK) 1720 1721 #define DDRC_PMLCB4_TRIGONSEL_MASK (0x3C000000U) 1722 #define DDRC_PMLCB4_TRIGONSEL_SHIFT (26U) 1723 #define DDRC_PMLCB4_TRIGONSEL_WIDTH (4U) 1724 #define DDRC_PMLCB4_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB4_TRIGONSEL_SHIFT)) & DDRC_PMLCB4_TRIGONSEL_MASK) 1725 /*! @} */ 1726 1727 /*! @name PMC4 - Performance Monitor Counter */ 1728 /*! @{ */ 1729 1730 #define DDRC_PMC4_PMC4_MASK (0xFFFFFFFFU) 1731 #define DDRC_PMC4_PMC4_SHIFT (0U) 1732 #define DDRC_PMC4_PMC4_WIDTH (32U) 1733 #define DDRC_PMC4_PMC4(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC4_PMC4_SHIFT)) & DDRC_PMC4_PMC4_MASK) 1734 /*! @} */ 1735 1736 /*! @name PMLCA5 - Performance Monitor Local Control A */ 1737 /*! @{ */ 1738 1739 #define DDRC_PMLCA5_BDIST_MASK (0x3FU) 1740 #define DDRC_PMLCA5_BDIST_SHIFT (0U) 1741 #define DDRC_PMLCA5_BDIST_WIDTH (6U) 1742 #define DDRC_PMLCA5_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BDIST_SHIFT)) & DDRC_PMLCA5_BDIST_MASK) 1743 1744 #define DDRC_PMLCA5_BGRAN_MASK (0x7C0U) 1745 #define DDRC_PMLCA5_BGRAN_SHIFT (6U) 1746 #define DDRC_PMLCA5_BGRAN_WIDTH (5U) 1747 #define DDRC_PMLCA5_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BGRAN_SHIFT)) & DDRC_PMLCA5_BGRAN_MASK) 1748 1749 #define DDRC_PMLCA5_BSIZE_MASK (0xF800U) 1750 #define DDRC_PMLCA5_BSIZE_SHIFT (11U) 1751 #define DDRC_PMLCA5_BSIZE_WIDTH (5U) 1752 #define DDRC_PMLCA5_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_BSIZE_SHIFT)) & DDRC_PMLCA5_BSIZE_MASK) 1753 1754 #define DDRC_PMLCA5_EVENT_MASK (0x7F0000U) 1755 #define DDRC_PMLCA5_EVENT_SHIFT (16U) 1756 #define DDRC_PMLCA5_EVENT_WIDTH (7U) 1757 #define DDRC_PMLCA5_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_EVENT_SHIFT)) & DDRC_PMLCA5_EVENT_MASK) 1758 1759 #define DDRC_PMLCA5_CE_MASK (0x4000000U) 1760 #define DDRC_PMLCA5_CE_SHIFT (26U) 1761 #define DDRC_PMLCA5_CE_WIDTH (1U) 1762 #define DDRC_PMLCA5_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_CE_SHIFT)) & DDRC_PMLCA5_CE_MASK) 1763 1764 #define DDRC_PMLCA5_FC_MASK (0x80000000U) 1765 #define DDRC_PMLCA5_FC_SHIFT (31U) 1766 #define DDRC_PMLCA5_FC_WIDTH (1U) 1767 #define DDRC_PMLCA5_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA5_FC_SHIFT)) & DDRC_PMLCA5_FC_MASK) 1768 /*! @} */ 1769 1770 /*! @name PMLCB5 - Performance Monitor Local Control B */ 1771 /*! @{ */ 1772 1773 #define DDRC_PMLCB5_THRESHOLD_MASK (0x3FU) 1774 #define DDRC_PMLCB5_THRESHOLD_SHIFT (0U) 1775 #define DDRC_PMLCB5_THRESHOLD_WIDTH (6U) 1776 #define DDRC_PMLCB5_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_THRESHOLD_SHIFT)) & DDRC_PMLCB5_THRESHOLD_MASK) 1777 1778 #define DDRC_PMLCB5_TBMULT_MASK (0x700U) 1779 #define DDRC_PMLCB5_TBMULT_SHIFT (8U) 1780 #define DDRC_PMLCB5_TBMULT_WIDTH (3U) 1781 #define DDRC_PMLCB5_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TBMULT_SHIFT)) & DDRC_PMLCB5_TBMULT_MASK) 1782 1783 #define DDRC_PMLCB5_TRIGOFFCNTL_MASK (0x30000U) 1784 #define DDRC_PMLCB5_TRIGOFFCNTL_SHIFT (16U) 1785 #define DDRC_PMLCB5_TRIGOFFCNTL_WIDTH (2U) 1786 #define DDRC_PMLCB5_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB5_TRIGOFFCNTL_MASK) 1787 1788 #define DDRC_PMLCB5_TRIGONCNTL_MASK (0xC0000U) 1789 #define DDRC_PMLCB5_TRIGONCNTL_SHIFT (18U) 1790 #define DDRC_PMLCB5_TRIGONCNTL_WIDTH (2U) 1791 #define DDRC_PMLCB5_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONCNTL_SHIFT)) & DDRC_PMLCB5_TRIGONCNTL_MASK) 1792 1793 #define DDRC_PMLCB5_TRIGOFFSEL_MASK (0xF00000U) 1794 #define DDRC_PMLCB5_TRIGOFFSEL_SHIFT (20U) 1795 #define DDRC_PMLCB5_TRIGOFFSEL_WIDTH (4U) 1796 #define DDRC_PMLCB5_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB5_TRIGOFFSEL_MASK) 1797 1798 #define DDRC_PMLCB5_TRIGONSEL_MASK (0x3C000000U) 1799 #define DDRC_PMLCB5_TRIGONSEL_SHIFT (26U) 1800 #define DDRC_PMLCB5_TRIGONSEL_WIDTH (4U) 1801 #define DDRC_PMLCB5_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB5_TRIGONSEL_SHIFT)) & DDRC_PMLCB5_TRIGONSEL_MASK) 1802 /*! @} */ 1803 1804 /*! @name PMC5 - Performance Monitor Counter */ 1805 /*! @{ */ 1806 1807 #define DDRC_PMC5_PMC5_MASK (0xFFFFFFFFU) 1808 #define DDRC_PMC5_PMC5_SHIFT (0U) 1809 #define DDRC_PMC5_PMC5_WIDTH (32U) 1810 #define DDRC_PMC5_PMC5(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC5_PMC5_SHIFT)) & DDRC_PMC5_PMC5_MASK) 1811 /*! @} */ 1812 1813 /*! @name PMLCA6 - Performance Monitor Local Control A */ 1814 /*! @{ */ 1815 1816 #define DDRC_PMLCA6_BDIST_MASK (0x3FU) 1817 #define DDRC_PMLCA6_BDIST_SHIFT (0U) 1818 #define DDRC_PMLCA6_BDIST_WIDTH (6U) 1819 #define DDRC_PMLCA6_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BDIST_SHIFT)) & DDRC_PMLCA6_BDIST_MASK) 1820 1821 #define DDRC_PMLCA6_BGRAN_MASK (0x7C0U) 1822 #define DDRC_PMLCA6_BGRAN_SHIFT (6U) 1823 #define DDRC_PMLCA6_BGRAN_WIDTH (5U) 1824 #define DDRC_PMLCA6_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BGRAN_SHIFT)) & DDRC_PMLCA6_BGRAN_MASK) 1825 1826 #define DDRC_PMLCA6_BSIZE_MASK (0xF800U) 1827 #define DDRC_PMLCA6_BSIZE_SHIFT (11U) 1828 #define DDRC_PMLCA6_BSIZE_WIDTH (5U) 1829 #define DDRC_PMLCA6_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_BSIZE_SHIFT)) & DDRC_PMLCA6_BSIZE_MASK) 1830 1831 #define DDRC_PMLCA6_EVENT_MASK (0x7F0000U) 1832 #define DDRC_PMLCA6_EVENT_SHIFT (16U) 1833 #define DDRC_PMLCA6_EVENT_WIDTH (7U) 1834 #define DDRC_PMLCA6_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_EVENT_SHIFT)) & DDRC_PMLCA6_EVENT_MASK) 1835 1836 #define DDRC_PMLCA6_CE_MASK (0x4000000U) 1837 #define DDRC_PMLCA6_CE_SHIFT (26U) 1838 #define DDRC_PMLCA6_CE_WIDTH (1U) 1839 #define DDRC_PMLCA6_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_CE_SHIFT)) & DDRC_PMLCA6_CE_MASK) 1840 1841 #define DDRC_PMLCA6_FC_MASK (0x80000000U) 1842 #define DDRC_PMLCA6_FC_SHIFT (31U) 1843 #define DDRC_PMLCA6_FC_WIDTH (1U) 1844 #define DDRC_PMLCA6_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA6_FC_SHIFT)) & DDRC_PMLCA6_FC_MASK) 1845 /*! @} */ 1846 1847 /*! @name PMLCB6 - Performance Monitor Local Control B */ 1848 /*! @{ */ 1849 1850 #define DDRC_PMLCB6_THRESHOLD_MASK (0x3FU) 1851 #define DDRC_PMLCB6_THRESHOLD_SHIFT (0U) 1852 #define DDRC_PMLCB6_THRESHOLD_WIDTH (6U) 1853 #define DDRC_PMLCB6_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_THRESHOLD_SHIFT)) & DDRC_PMLCB6_THRESHOLD_MASK) 1854 1855 #define DDRC_PMLCB6_TBMULT_MASK (0x700U) 1856 #define DDRC_PMLCB6_TBMULT_SHIFT (8U) 1857 #define DDRC_PMLCB6_TBMULT_WIDTH (3U) 1858 #define DDRC_PMLCB6_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TBMULT_SHIFT)) & DDRC_PMLCB6_TBMULT_MASK) 1859 1860 #define DDRC_PMLCB6_TRIGOFFCNTL_MASK (0x30000U) 1861 #define DDRC_PMLCB6_TRIGOFFCNTL_SHIFT (16U) 1862 #define DDRC_PMLCB6_TRIGOFFCNTL_WIDTH (2U) 1863 #define DDRC_PMLCB6_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB6_TRIGOFFCNTL_MASK) 1864 1865 #define DDRC_PMLCB6_TRIGONCNTL_MASK (0xC0000U) 1866 #define DDRC_PMLCB6_TRIGONCNTL_SHIFT (18U) 1867 #define DDRC_PMLCB6_TRIGONCNTL_WIDTH (2U) 1868 #define DDRC_PMLCB6_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONCNTL_SHIFT)) & DDRC_PMLCB6_TRIGONCNTL_MASK) 1869 1870 #define DDRC_PMLCB6_TRIGOFFSEL_MASK (0xF00000U) 1871 #define DDRC_PMLCB6_TRIGOFFSEL_SHIFT (20U) 1872 #define DDRC_PMLCB6_TRIGOFFSEL_WIDTH (4U) 1873 #define DDRC_PMLCB6_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB6_TRIGOFFSEL_MASK) 1874 1875 #define DDRC_PMLCB6_TRIGONSEL_MASK (0x3C000000U) 1876 #define DDRC_PMLCB6_TRIGONSEL_SHIFT (26U) 1877 #define DDRC_PMLCB6_TRIGONSEL_WIDTH (4U) 1878 #define DDRC_PMLCB6_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB6_TRIGONSEL_SHIFT)) & DDRC_PMLCB6_TRIGONSEL_MASK) 1879 /*! @} */ 1880 1881 /*! @name PMC6 - Performance Monitor Counter */ 1882 /*! @{ */ 1883 1884 #define DDRC_PMC6_PMC6_MASK (0xFFFFFFFFU) 1885 #define DDRC_PMC6_PMC6_SHIFT (0U) 1886 #define DDRC_PMC6_PMC6_WIDTH (32U) 1887 #define DDRC_PMC6_PMC6(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC6_PMC6_SHIFT)) & DDRC_PMC6_PMC6_MASK) 1888 /*! @} */ 1889 1890 /*! @name PMLCA7 - Performance Monitor Local Control A */ 1891 /*! @{ */ 1892 1893 #define DDRC_PMLCA7_BDIST_MASK (0x3FU) 1894 #define DDRC_PMLCA7_BDIST_SHIFT (0U) 1895 #define DDRC_PMLCA7_BDIST_WIDTH (6U) 1896 #define DDRC_PMLCA7_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BDIST_SHIFT)) & DDRC_PMLCA7_BDIST_MASK) 1897 1898 #define DDRC_PMLCA7_BGRAN_MASK (0x7C0U) 1899 #define DDRC_PMLCA7_BGRAN_SHIFT (6U) 1900 #define DDRC_PMLCA7_BGRAN_WIDTH (5U) 1901 #define DDRC_PMLCA7_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BGRAN_SHIFT)) & DDRC_PMLCA7_BGRAN_MASK) 1902 1903 #define DDRC_PMLCA7_BSIZE_MASK (0xF800U) 1904 #define DDRC_PMLCA7_BSIZE_SHIFT (11U) 1905 #define DDRC_PMLCA7_BSIZE_WIDTH (5U) 1906 #define DDRC_PMLCA7_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_BSIZE_SHIFT)) & DDRC_PMLCA7_BSIZE_MASK) 1907 1908 #define DDRC_PMLCA7_EVENT_MASK (0x7F0000U) 1909 #define DDRC_PMLCA7_EVENT_SHIFT (16U) 1910 #define DDRC_PMLCA7_EVENT_WIDTH (7U) 1911 #define DDRC_PMLCA7_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_EVENT_SHIFT)) & DDRC_PMLCA7_EVENT_MASK) 1912 1913 #define DDRC_PMLCA7_CE_MASK (0x4000000U) 1914 #define DDRC_PMLCA7_CE_SHIFT (26U) 1915 #define DDRC_PMLCA7_CE_WIDTH (1U) 1916 #define DDRC_PMLCA7_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_CE_SHIFT)) & DDRC_PMLCA7_CE_MASK) 1917 1918 #define DDRC_PMLCA7_FC_MASK (0x80000000U) 1919 #define DDRC_PMLCA7_FC_SHIFT (31U) 1920 #define DDRC_PMLCA7_FC_WIDTH (1U) 1921 #define DDRC_PMLCA7_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA7_FC_SHIFT)) & DDRC_PMLCA7_FC_MASK) 1922 /*! @} */ 1923 1924 /*! @name PMLCB7 - Performance Monitor Local Control B */ 1925 /*! @{ */ 1926 1927 #define DDRC_PMLCB7_THRESHOLD_MASK (0x3FU) 1928 #define DDRC_PMLCB7_THRESHOLD_SHIFT (0U) 1929 #define DDRC_PMLCB7_THRESHOLD_WIDTH (6U) 1930 #define DDRC_PMLCB7_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_THRESHOLD_SHIFT)) & DDRC_PMLCB7_THRESHOLD_MASK) 1931 1932 #define DDRC_PMLCB7_TBMULT_MASK (0x700U) 1933 #define DDRC_PMLCB7_TBMULT_SHIFT (8U) 1934 #define DDRC_PMLCB7_TBMULT_WIDTH (3U) 1935 #define DDRC_PMLCB7_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TBMULT_SHIFT)) & DDRC_PMLCB7_TBMULT_MASK) 1936 1937 #define DDRC_PMLCB7_TRIGOFFCNTL_MASK (0x30000U) 1938 #define DDRC_PMLCB7_TRIGOFFCNTL_SHIFT (16U) 1939 #define DDRC_PMLCB7_TRIGOFFCNTL_WIDTH (2U) 1940 #define DDRC_PMLCB7_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB7_TRIGOFFCNTL_MASK) 1941 1942 #define DDRC_PMLCB7_TRIGONCNTL_MASK (0xC0000U) 1943 #define DDRC_PMLCB7_TRIGONCNTL_SHIFT (18U) 1944 #define DDRC_PMLCB7_TRIGONCNTL_WIDTH (2U) 1945 #define DDRC_PMLCB7_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONCNTL_SHIFT)) & DDRC_PMLCB7_TRIGONCNTL_MASK) 1946 1947 #define DDRC_PMLCB7_TRIGOFFSEL_MASK (0xF00000U) 1948 #define DDRC_PMLCB7_TRIGOFFSEL_SHIFT (20U) 1949 #define DDRC_PMLCB7_TRIGOFFSEL_WIDTH (4U) 1950 #define DDRC_PMLCB7_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB7_TRIGOFFSEL_MASK) 1951 1952 #define DDRC_PMLCB7_TRIGONSEL_MASK (0x3C000000U) 1953 #define DDRC_PMLCB7_TRIGONSEL_SHIFT (26U) 1954 #define DDRC_PMLCB7_TRIGONSEL_WIDTH (4U) 1955 #define DDRC_PMLCB7_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB7_TRIGONSEL_SHIFT)) & DDRC_PMLCB7_TRIGONSEL_MASK) 1956 /*! @} */ 1957 1958 /*! @name PMC7 - Performance Monitor Counter */ 1959 /*! @{ */ 1960 1961 #define DDRC_PMC7_PMC7_MASK (0xFFFFFFFFU) 1962 #define DDRC_PMC7_PMC7_SHIFT (0U) 1963 #define DDRC_PMC7_PMC7_WIDTH (32U) 1964 #define DDRC_PMC7_PMC7(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC7_PMC7_SHIFT)) & DDRC_PMC7_PMC7_MASK) 1965 /*! @} */ 1966 1967 /*! @name PMLCA8 - Performance Monitor Local Control A */ 1968 /*! @{ */ 1969 1970 #define DDRC_PMLCA8_BDIST_MASK (0x3FU) 1971 #define DDRC_PMLCA8_BDIST_SHIFT (0U) 1972 #define DDRC_PMLCA8_BDIST_WIDTH (6U) 1973 #define DDRC_PMLCA8_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BDIST_SHIFT)) & DDRC_PMLCA8_BDIST_MASK) 1974 1975 #define DDRC_PMLCA8_BGRAN_MASK (0x7C0U) 1976 #define DDRC_PMLCA8_BGRAN_SHIFT (6U) 1977 #define DDRC_PMLCA8_BGRAN_WIDTH (5U) 1978 #define DDRC_PMLCA8_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BGRAN_SHIFT)) & DDRC_PMLCA8_BGRAN_MASK) 1979 1980 #define DDRC_PMLCA8_BSIZE_MASK (0xF800U) 1981 #define DDRC_PMLCA8_BSIZE_SHIFT (11U) 1982 #define DDRC_PMLCA8_BSIZE_WIDTH (5U) 1983 #define DDRC_PMLCA8_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_BSIZE_SHIFT)) & DDRC_PMLCA8_BSIZE_MASK) 1984 1985 #define DDRC_PMLCA8_EVENT_MASK (0x7F0000U) 1986 #define DDRC_PMLCA8_EVENT_SHIFT (16U) 1987 #define DDRC_PMLCA8_EVENT_WIDTH (7U) 1988 #define DDRC_PMLCA8_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_EVENT_SHIFT)) & DDRC_PMLCA8_EVENT_MASK) 1989 1990 #define DDRC_PMLCA8_CE_MASK (0x4000000U) 1991 #define DDRC_PMLCA8_CE_SHIFT (26U) 1992 #define DDRC_PMLCA8_CE_WIDTH (1U) 1993 #define DDRC_PMLCA8_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_CE_SHIFT)) & DDRC_PMLCA8_CE_MASK) 1994 1995 #define DDRC_PMLCA8_FC_MASK (0x80000000U) 1996 #define DDRC_PMLCA8_FC_SHIFT (31U) 1997 #define DDRC_PMLCA8_FC_WIDTH (1U) 1998 #define DDRC_PMLCA8_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA8_FC_SHIFT)) & DDRC_PMLCA8_FC_MASK) 1999 /*! @} */ 2000 2001 /*! @name PMLCB8 - Performance Monitor Local Control B */ 2002 /*! @{ */ 2003 2004 #define DDRC_PMLCB8_THRESHOLD_MASK (0x3FU) 2005 #define DDRC_PMLCB8_THRESHOLD_SHIFT (0U) 2006 #define DDRC_PMLCB8_THRESHOLD_WIDTH (6U) 2007 #define DDRC_PMLCB8_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_THRESHOLD_SHIFT)) & DDRC_PMLCB8_THRESHOLD_MASK) 2008 2009 #define DDRC_PMLCB8_TBMULT_MASK (0x700U) 2010 #define DDRC_PMLCB8_TBMULT_SHIFT (8U) 2011 #define DDRC_PMLCB8_TBMULT_WIDTH (3U) 2012 #define DDRC_PMLCB8_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TBMULT_SHIFT)) & DDRC_PMLCB8_TBMULT_MASK) 2013 2014 #define DDRC_PMLCB8_TRIGOFFCNTL_MASK (0x30000U) 2015 #define DDRC_PMLCB8_TRIGOFFCNTL_SHIFT (16U) 2016 #define DDRC_PMLCB8_TRIGOFFCNTL_WIDTH (2U) 2017 #define DDRC_PMLCB8_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB8_TRIGOFFCNTL_MASK) 2018 2019 #define DDRC_PMLCB8_TRIGONCNTL_MASK (0xC0000U) 2020 #define DDRC_PMLCB8_TRIGONCNTL_SHIFT (18U) 2021 #define DDRC_PMLCB8_TRIGONCNTL_WIDTH (2U) 2022 #define DDRC_PMLCB8_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONCNTL_SHIFT)) & DDRC_PMLCB8_TRIGONCNTL_MASK) 2023 2024 #define DDRC_PMLCB8_TRIGOFFSEL_MASK (0xF00000U) 2025 #define DDRC_PMLCB8_TRIGOFFSEL_SHIFT (20U) 2026 #define DDRC_PMLCB8_TRIGOFFSEL_WIDTH (4U) 2027 #define DDRC_PMLCB8_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB8_TRIGOFFSEL_MASK) 2028 2029 #define DDRC_PMLCB8_TRIGONSEL_MASK (0x3C000000U) 2030 #define DDRC_PMLCB8_TRIGONSEL_SHIFT (26U) 2031 #define DDRC_PMLCB8_TRIGONSEL_WIDTH (4U) 2032 #define DDRC_PMLCB8_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB8_TRIGONSEL_SHIFT)) & DDRC_PMLCB8_TRIGONSEL_MASK) 2033 /*! @} */ 2034 2035 /*! @name PMC8 - Performance Monitor Counter */ 2036 /*! @{ */ 2037 2038 #define DDRC_PMC8_PMC8_MASK (0xFFFFFFFFU) 2039 #define DDRC_PMC8_PMC8_SHIFT (0U) 2040 #define DDRC_PMC8_PMC8_WIDTH (32U) 2041 #define DDRC_PMC8_PMC8(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC8_PMC8_SHIFT)) & DDRC_PMC8_PMC8_MASK) 2042 /*! @} */ 2043 2044 /*! @name PMLCA9 - Performance Monitor Local Control A */ 2045 /*! @{ */ 2046 2047 #define DDRC_PMLCA9_BDIST_MASK (0x3FU) 2048 #define DDRC_PMLCA9_BDIST_SHIFT (0U) 2049 #define DDRC_PMLCA9_BDIST_WIDTH (6U) 2050 #define DDRC_PMLCA9_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BDIST_SHIFT)) & DDRC_PMLCA9_BDIST_MASK) 2051 2052 #define DDRC_PMLCA9_BGRAN_MASK (0x7C0U) 2053 #define DDRC_PMLCA9_BGRAN_SHIFT (6U) 2054 #define DDRC_PMLCA9_BGRAN_WIDTH (5U) 2055 #define DDRC_PMLCA9_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BGRAN_SHIFT)) & DDRC_PMLCA9_BGRAN_MASK) 2056 2057 #define DDRC_PMLCA9_BSIZE_MASK (0xF800U) 2058 #define DDRC_PMLCA9_BSIZE_SHIFT (11U) 2059 #define DDRC_PMLCA9_BSIZE_WIDTH (5U) 2060 #define DDRC_PMLCA9_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_BSIZE_SHIFT)) & DDRC_PMLCA9_BSIZE_MASK) 2061 2062 #define DDRC_PMLCA9_EVENT_MASK (0x7F0000U) 2063 #define DDRC_PMLCA9_EVENT_SHIFT (16U) 2064 #define DDRC_PMLCA9_EVENT_WIDTH (7U) 2065 #define DDRC_PMLCA9_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_EVENT_SHIFT)) & DDRC_PMLCA9_EVENT_MASK) 2066 2067 #define DDRC_PMLCA9_CE_MASK (0x4000000U) 2068 #define DDRC_PMLCA9_CE_SHIFT (26U) 2069 #define DDRC_PMLCA9_CE_WIDTH (1U) 2070 #define DDRC_PMLCA9_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_CE_SHIFT)) & DDRC_PMLCA9_CE_MASK) 2071 2072 #define DDRC_PMLCA9_FC_MASK (0x80000000U) 2073 #define DDRC_PMLCA9_FC_SHIFT (31U) 2074 #define DDRC_PMLCA9_FC_WIDTH (1U) 2075 #define DDRC_PMLCA9_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA9_FC_SHIFT)) & DDRC_PMLCA9_FC_MASK) 2076 /*! @} */ 2077 2078 /*! @name PMLCB9 - Performance Monitor Local Control B */ 2079 /*! @{ */ 2080 2081 #define DDRC_PMLCB9_THRESHOLD_MASK (0x3FU) 2082 #define DDRC_PMLCB9_THRESHOLD_SHIFT (0U) 2083 #define DDRC_PMLCB9_THRESHOLD_WIDTH (6U) 2084 #define DDRC_PMLCB9_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_THRESHOLD_SHIFT)) & DDRC_PMLCB9_THRESHOLD_MASK) 2085 2086 #define DDRC_PMLCB9_TBMULT_MASK (0x700U) 2087 #define DDRC_PMLCB9_TBMULT_SHIFT (8U) 2088 #define DDRC_PMLCB9_TBMULT_WIDTH (3U) 2089 #define DDRC_PMLCB9_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TBMULT_SHIFT)) & DDRC_PMLCB9_TBMULT_MASK) 2090 2091 #define DDRC_PMLCB9_TRIGOFFCNTL_MASK (0x30000U) 2092 #define DDRC_PMLCB9_TRIGOFFCNTL_SHIFT (16U) 2093 #define DDRC_PMLCB9_TRIGOFFCNTL_WIDTH (2U) 2094 #define DDRC_PMLCB9_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB9_TRIGOFFCNTL_MASK) 2095 2096 #define DDRC_PMLCB9_TRIGONCNTL_MASK (0xC0000U) 2097 #define DDRC_PMLCB9_TRIGONCNTL_SHIFT (18U) 2098 #define DDRC_PMLCB9_TRIGONCNTL_WIDTH (2U) 2099 #define DDRC_PMLCB9_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONCNTL_SHIFT)) & DDRC_PMLCB9_TRIGONCNTL_MASK) 2100 2101 #define DDRC_PMLCB9_TRIGOFFSEL_MASK (0xF00000U) 2102 #define DDRC_PMLCB9_TRIGOFFSEL_SHIFT (20U) 2103 #define DDRC_PMLCB9_TRIGOFFSEL_WIDTH (4U) 2104 #define DDRC_PMLCB9_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB9_TRIGOFFSEL_MASK) 2105 2106 #define DDRC_PMLCB9_TRIGONSEL_MASK (0x3C000000U) 2107 #define DDRC_PMLCB9_TRIGONSEL_SHIFT (26U) 2108 #define DDRC_PMLCB9_TRIGONSEL_WIDTH (4U) 2109 #define DDRC_PMLCB9_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB9_TRIGONSEL_SHIFT)) & DDRC_PMLCB9_TRIGONSEL_MASK) 2110 /*! @} */ 2111 2112 /*! @name PMC9 - Performance Monitor Counter */ 2113 /*! @{ */ 2114 2115 #define DDRC_PMC9_PMC9_MASK (0xFFFFFFFFU) 2116 #define DDRC_PMC9_PMC9_SHIFT (0U) 2117 #define DDRC_PMC9_PMC9_WIDTH (32U) 2118 #define DDRC_PMC9_PMC9(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC9_PMC9_SHIFT)) & DDRC_PMC9_PMC9_MASK) 2119 /*! @} */ 2120 2121 /*! @name PMLCA10 - Performance Monitor Local Control A */ 2122 /*! @{ */ 2123 2124 #define DDRC_PMLCA10_BDIST_MASK (0x3FU) 2125 #define DDRC_PMLCA10_BDIST_SHIFT (0U) 2126 #define DDRC_PMLCA10_BDIST_WIDTH (6U) 2127 #define DDRC_PMLCA10_BDIST(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BDIST_SHIFT)) & DDRC_PMLCA10_BDIST_MASK) 2128 2129 #define DDRC_PMLCA10_BGRAN_MASK (0x7C0U) 2130 #define DDRC_PMLCA10_BGRAN_SHIFT (6U) 2131 #define DDRC_PMLCA10_BGRAN_WIDTH (5U) 2132 #define DDRC_PMLCA10_BGRAN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BGRAN_SHIFT)) & DDRC_PMLCA10_BGRAN_MASK) 2133 2134 #define DDRC_PMLCA10_BSIZE_MASK (0xF800U) 2135 #define DDRC_PMLCA10_BSIZE_SHIFT (11U) 2136 #define DDRC_PMLCA10_BSIZE_WIDTH (5U) 2137 #define DDRC_PMLCA10_BSIZE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_BSIZE_SHIFT)) & DDRC_PMLCA10_BSIZE_MASK) 2138 2139 #define DDRC_PMLCA10_EVENT_MASK (0x7F0000U) 2140 #define DDRC_PMLCA10_EVENT_SHIFT (16U) 2141 #define DDRC_PMLCA10_EVENT_WIDTH (7U) 2142 #define DDRC_PMLCA10_EVENT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_EVENT_SHIFT)) & DDRC_PMLCA10_EVENT_MASK) 2143 2144 #define DDRC_PMLCA10_CE_MASK (0x4000000U) 2145 #define DDRC_PMLCA10_CE_SHIFT (26U) 2146 #define DDRC_PMLCA10_CE_WIDTH (1U) 2147 #define DDRC_PMLCA10_CE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_CE_SHIFT)) & DDRC_PMLCA10_CE_MASK) 2148 2149 #define DDRC_PMLCA10_FC_MASK (0x80000000U) 2150 #define DDRC_PMLCA10_FC_SHIFT (31U) 2151 #define DDRC_PMLCA10_FC_WIDTH (1U) 2152 #define DDRC_PMLCA10_FC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCA10_FC_SHIFT)) & DDRC_PMLCA10_FC_MASK) 2153 /*! @} */ 2154 2155 /*! @name PMLCB10 - Performance Monitor Local Control B */ 2156 /*! @{ */ 2157 2158 #define DDRC_PMLCB10_THRESHOLD_MASK (0x3FU) 2159 #define DDRC_PMLCB10_THRESHOLD_SHIFT (0U) 2160 #define DDRC_PMLCB10_THRESHOLD_WIDTH (6U) 2161 #define DDRC_PMLCB10_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_THRESHOLD_SHIFT)) & DDRC_PMLCB10_THRESHOLD_MASK) 2162 2163 #define DDRC_PMLCB10_TBMULT_MASK (0x700U) 2164 #define DDRC_PMLCB10_TBMULT_SHIFT (8U) 2165 #define DDRC_PMLCB10_TBMULT_WIDTH (3U) 2166 #define DDRC_PMLCB10_TBMULT(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TBMULT_SHIFT)) & DDRC_PMLCB10_TBMULT_MASK) 2167 2168 #define DDRC_PMLCB10_TRIGOFFCNTL_MASK (0x30000U) 2169 #define DDRC_PMLCB10_TRIGOFFCNTL_SHIFT (16U) 2170 #define DDRC_PMLCB10_TRIGOFFCNTL_WIDTH (2U) 2171 #define DDRC_PMLCB10_TRIGOFFCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFCNTL_SHIFT)) & DDRC_PMLCB10_TRIGOFFCNTL_MASK) 2172 2173 #define DDRC_PMLCB10_TRIGONCNTL_MASK (0xC0000U) 2174 #define DDRC_PMLCB10_TRIGONCNTL_SHIFT (18U) 2175 #define DDRC_PMLCB10_TRIGONCNTL_WIDTH (2U) 2176 #define DDRC_PMLCB10_TRIGONCNTL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONCNTL_SHIFT)) & DDRC_PMLCB10_TRIGONCNTL_MASK) 2177 2178 #define DDRC_PMLCB10_TRIGOFFSEL_MASK (0xF00000U) 2179 #define DDRC_PMLCB10_TRIGOFFSEL_SHIFT (20U) 2180 #define DDRC_PMLCB10_TRIGOFFSEL_WIDTH (4U) 2181 #define DDRC_PMLCB10_TRIGOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGOFFSEL_SHIFT)) & DDRC_PMLCB10_TRIGOFFSEL_MASK) 2182 2183 #define DDRC_PMLCB10_TRIGONSEL_MASK (0x3C000000U) 2184 #define DDRC_PMLCB10_TRIGONSEL_SHIFT (26U) 2185 #define DDRC_PMLCB10_TRIGONSEL_WIDTH (4U) 2186 #define DDRC_PMLCB10_TRIGONSEL(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMLCB10_TRIGONSEL_SHIFT)) & DDRC_PMLCB10_TRIGONSEL_MASK) 2187 /*! @} */ 2188 2189 /*! @name PMC10 - Performance Monitor Counter */ 2190 /*! @{ */ 2191 2192 #define DDRC_PMC10_PMC10_MASK (0xFFFFFFFFU) 2193 #define DDRC_PMC10_PMC10_SHIFT (0U) 2194 #define DDRC_PMC10_PMC10_WIDTH (32U) 2195 #define DDRC_PMC10_PMC10(x) (((uint32_t)(((uint32_t)(x)) << DDRC_PMC10_PMC10_SHIFT)) & DDRC_PMC10_PMC10_MASK) 2196 /*! @} */ 2197 2198 /*! @name ERR_EN - Error Enable */ 2199 /*! @{ */ 2200 2201 #define DDRC_ERR_EN_WTE_EN_MASK (0x1U) 2202 #define DDRC_ERR_EN_WTE_EN_SHIFT (0U) 2203 #define DDRC_ERR_EN_WTE_EN_WIDTH (1U) 2204 #define DDRC_ERR_EN_WTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_WTE_EN_SHIFT)) & DDRC_ERR_EN_WTE_EN_MASK) 2205 2206 #define DDRC_ERR_EN_RTE_EN_MASK (0x2U) 2207 #define DDRC_ERR_EN_RTE_EN_SHIFT (1U) 2208 #define DDRC_ERR_EN_RTE_EN_WIDTH (1U) 2209 #define DDRC_ERR_EN_RTE_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_RTE_EN_SHIFT)) & DDRC_ERR_EN_RTE_EN_MASK) 2210 2211 #define DDRC_ERR_EN_LKSTP_2_EN_MASK (0x4U) 2212 #define DDRC_ERR_EN_LKSTP_2_EN_SHIFT (2U) 2213 #define DDRC_ERR_EN_LKSTP_2_EN_WIDTH (1U) 2214 #define DDRC_ERR_EN_LKSTP_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_LKSTP_2_EN_SHIFT)) & DDRC_ERR_EN_LKSTP_2_EN_MASK) 2215 2216 #define DDRC_ERR_EN_LKSTP_1_EN_MASK (0x8U) 2217 #define DDRC_ERR_EN_LKSTP_1_EN_SHIFT (3U) 2218 #define DDRC_ERR_EN_LKSTP_1_EN_WIDTH (1U) 2219 #define DDRC_ERR_EN_LKSTP_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_LKSTP_1_EN_SHIFT)) & DDRC_ERR_EN_LKSTP_1_EN_MASK) 2220 2221 #define DDRC_ERR_EN_PAR_1_EN_MASK (0x20U) 2222 #define DDRC_ERR_EN_PAR_1_EN_SHIFT (5U) 2223 #define DDRC_ERR_EN_PAR_1_EN_WIDTH (1U) 2224 #define DDRC_ERR_EN_PAR_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_PAR_1_EN_SHIFT)) & DDRC_ERR_EN_PAR_1_EN_MASK) 2225 2226 #define DDRC_ERR_EN_ECC_EN_RAM_2_MASK (0x40U) 2227 #define DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT (6U) 2228 #define DDRC_ERR_EN_ECC_EN_RAM_2_WIDTH (1U) 2229 #define DDRC_ERR_EN_ECC_EN_RAM_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_2_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_2_MASK) 2230 2231 #define DDRC_ERR_EN_ECC_EN_RAM_1_MASK (0x80U) 2232 #define DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT (7U) 2233 #define DDRC_ERR_EN_ECC_EN_RAM_1_WIDTH (1U) 2234 #define DDRC_ERR_EN_ECC_EN_RAM_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_RAM_1_SHIFT)) & DDRC_ERR_EN_ECC_EN_RAM_1_MASK) 2235 2236 #define DDRC_ERR_EN_CRC_2_EN_MASK (0x100U) 2237 #define DDRC_ERR_EN_CRC_2_EN_SHIFT (8U) 2238 #define DDRC_ERR_EN_CRC_2_EN_WIDTH (1U) 2239 #define DDRC_ERR_EN_CRC_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_CRC_2_EN_SHIFT)) & DDRC_ERR_EN_CRC_2_EN_MASK) 2240 2241 #define DDRC_ERR_EN_CRC_1_EN_MASK (0x200U) 2242 #define DDRC_ERR_EN_CRC_1_EN_SHIFT (9U) 2243 #define DDRC_ERR_EN_CRC_1_EN_WIDTH (1U) 2244 #define DDRC_ERR_EN_CRC_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_CRC_1_EN_SHIFT)) & DDRC_ERR_EN_CRC_1_EN_MASK) 2245 2246 #define DDRC_ERR_EN_INLINE_ECC_EN_MASK (0x40000000U) 2247 #define DDRC_ERR_EN_INLINE_ECC_EN_SHIFT (30U) 2248 #define DDRC_ERR_EN_INLINE_ECC_EN_WIDTH (1U) 2249 #define DDRC_ERR_EN_INLINE_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_INLINE_ECC_EN_SHIFT)) & DDRC_ERR_EN_INLINE_ECC_EN_MASK) 2250 2251 #define DDRC_ERR_EN_ECC_EN_MASK (0x80000000U) 2252 #define DDRC_ERR_EN_ECC_EN_SHIFT (31U) 2253 #define DDRC_ERR_EN_ECC_EN_WIDTH (1U) 2254 #define DDRC_ERR_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_EN_ECC_EN_SHIFT)) & DDRC_ERR_EN_ECC_EN_MASK) 2255 /*! @} */ 2256 2257 /*! @name DATA_ERR_INJECT_HI - Memory Data Path Error Injection Mask High */ 2258 /*! @{ */ 2259 2260 #define DDRC_DATA_ERR_INJECT_HI_EIMH_MASK (0xFFFFFFFFU) 2261 #define DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT (0U) 2262 #define DDRC_DATA_ERR_INJECT_HI_EIMH_WIDTH (32U) 2263 #define DDRC_DATA_ERR_INJECT_HI_EIMH(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_HI_EIMH_SHIFT)) & DDRC_DATA_ERR_INJECT_HI_EIMH_MASK) 2264 /*! @} */ 2265 2266 /*! @name DATA_ERR_INJECT_LO - Memory Data Path Error Injection Mask Low */ 2267 /*! @{ */ 2268 2269 #define DDRC_DATA_ERR_INJECT_LO_EIML_MASK (0xFFFFFFFFU) 2270 #define DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT (0U) 2271 #define DDRC_DATA_ERR_INJECT_LO_EIML_WIDTH (32U) 2272 #define DDRC_DATA_ERR_INJECT_LO_EIML(x) (((uint32_t)(((uint32_t)(x)) << DDRC_DATA_ERR_INJECT_LO_EIML_SHIFT)) & DDRC_DATA_ERR_INJECT_LO_EIML_MASK) 2273 /*! @} */ 2274 2275 /*! @name ERR_INJECT - Memory Data Path Error Injection Mask ECC */ 2276 /*! @{ */ 2277 2278 #define DDRC_ERR_INJECT_EEIM_MASK (0xFFU) 2279 #define DDRC_ERR_INJECT_EEIM_SHIFT (0U) 2280 #define DDRC_ERR_INJECT_EEIM_WIDTH (8U) 2281 #define DDRC_ERR_INJECT_EEIM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EEIM_SHIFT)) & DDRC_ERR_INJECT_EEIM_MASK) 2282 2283 #define DDRC_ERR_INJECT_EIEN_MASK (0x100U) 2284 #define DDRC_ERR_INJECT_EIEN_SHIFT (8U) 2285 #define DDRC_ERR_INJECT_EIEN_WIDTH (1U) 2286 #define DDRC_ERR_INJECT_EIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_EIEN_SHIFT)) & DDRC_ERR_INJECT_EIEN_MASK) 2287 2288 #define DDRC_ERR_INJECT_NUM_ECC_INJ_MASK (0xF000U) 2289 #define DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT (12U) 2290 #define DDRC_ERR_INJECT_NUM_ECC_INJ_WIDTH (4U) 2291 #define DDRC_ERR_INJECT_NUM_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_NUM_ECC_INJ_SHIFT)) & DDRC_ERR_INJECT_NUM_ECC_INJ_MASK) 2292 2293 #define DDRC_ERR_INJECT_PIEN_MASK (0x10000U) 2294 #define DDRC_ERR_INJECT_PIEN_SHIFT (16U) 2295 #define DDRC_ERR_INJECT_PIEN_WIDTH (1U) 2296 #define DDRC_ERR_INJECT_PIEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_PIEN_SHIFT)) & DDRC_ERR_INJECT_PIEN_MASK) 2297 2298 #define DDRC_ERR_INJECT_INTEIN_MASK (0x20000U) 2299 #define DDRC_ERR_INJECT_INTEIN_SHIFT (17U) 2300 #define DDRC_ERR_INJECT_INTEIN_WIDTH (1U) 2301 #define DDRC_ERR_INJECT_INTEIN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_INTEIN_SHIFT)) & DDRC_ERR_INJECT_INTEIN_MASK) 2302 2303 #define DDRC_ERR_INJECT_INTIES_MASK (0x1C0000U) 2304 #define DDRC_ERR_INJECT_INTIES_SHIFT (18U) 2305 #define DDRC_ERR_INJECT_INTIES_WIDTH (3U) 2306 #define DDRC_ERR_INJECT_INTIES(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_INTIES_SHIFT)) & DDRC_ERR_INJECT_INTIES_MASK) 2307 2308 #define DDRC_ERR_INJECT_ECC_INJ_SRC_MASK (0x600000U) 2309 #define DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT (21U) 2310 #define DDRC_ERR_INJECT_ECC_INJ_SRC_WIDTH (2U) 2311 #define DDRC_ERR_INJECT_ECC_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ECC_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_ECC_INJ_SRC_MASK) 2312 2313 #define DDRC_ERR_INJECT_FRC2B_MASK (0x800000U) 2314 #define DDRC_ERR_INJECT_FRC2B_SHIFT (23U) 2315 #define DDRC_ERR_INJECT_FRC2B_WIDTH (1U) 2316 #define DDRC_ERR_INJECT_FRC2B(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_FRC2B_SHIFT)) & DDRC_ERR_INJECT_FRC2B_MASK) 2317 2318 #define DDRC_ERR_INJECT_PAR_INJ_SRC_MASK (0x3000000U) 2319 #define DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT (24U) 2320 #define DDRC_ERR_INJECT_PAR_INJ_SRC_WIDTH (2U) 2321 #define DDRC_ERR_INJECT_PAR_INJ_SRC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_PAR_INJ_SRC_SHIFT)) & DDRC_ERR_INJECT_PAR_INJ_SRC_MASK) 2322 2323 #define DDRC_ERR_INJECT_ADDR_TEN_MASK (0x80000000U) 2324 #define DDRC_ERR_INJECT_ADDR_TEN_SHIFT (31U) 2325 #define DDRC_ERR_INJECT_ADDR_TEN_WIDTH (1U) 2326 #define DDRC_ERR_INJECT_ADDR_TEN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INJECT_ADDR_TEN_SHIFT)) & DDRC_ERR_INJECT_ADDR_TEN_MASK) 2327 /*! @} */ 2328 2329 /*! @name ADDR_ERR_INJ - Address Error Inject */ 2330 /*! @{ */ 2331 2332 #define DDRC_ADDR_ERR_INJ_ADDR_MASK (0xFFFFFFFFU) 2333 #define DDRC_ADDR_ERR_INJ_ADDR_SHIFT (0U) 2334 #define DDRC_ADDR_ERR_INJ_ADDR_WIDTH (32U) 2335 #define DDRC_ADDR_ERR_INJ_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ADDR_ERR_INJ_ADDR_SHIFT)) & DDRC_ADDR_ERR_INJ_ADDR_MASK) 2336 /*! @} */ 2337 2338 /*! @name CAPTURE_EXT_DATA_HI - Memory Extended Data Path Read Capture High */ 2339 /*! @{ */ 2340 2341 #define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK (0xFFFFFFFFU) 2342 #define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT (0U) 2343 #define DDRC_CAPTURE_EXT_DATA_HI_ECEHD_WIDTH (32U) 2344 #define DDRC_CAPTURE_EXT_DATA_HI_ECEHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_HI_ECEHD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_HI_ECEHD_MASK) 2345 /*! @} */ 2346 2347 /*! @name CAPTURE_EXT_DATA_LO - Memory Extended Data Path Read Capture Low */ 2348 /*! @{ */ 2349 2350 #define DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK (0xFFFFFFFFU) 2351 #define DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT (0U) 2352 #define DDRC_CAPTURE_EXT_DATA_LO_ECELD_WIDTH (32U) 2353 #define DDRC_CAPTURE_EXT_DATA_LO_ECELD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_DATA_LO_ECELD_SHIFT)) & DDRC_CAPTURE_EXT_DATA_LO_ECELD_MASK) 2354 /*! @} */ 2355 2356 /*! @name CAPTURE_DATA_HI - Memory Data Path Read Capture High */ 2357 /*! @{ */ 2358 2359 #define DDRC_CAPTURE_DATA_HI_ECHD_MASK (0xFFFFFFFFU) 2360 #define DDRC_CAPTURE_DATA_HI_ECHD_SHIFT (0U) 2361 #define DDRC_CAPTURE_DATA_HI_ECHD_WIDTH (32U) 2362 #define DDRC_CAPTURE_DATA_HI_ECHD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_HI_ECHD_SHIFT)) & DDRC_CAPTURE_DATA_HI_ECHD_MASK) 2363 /*! @} */ 2364 2365 /*! @name CAPTURE_DATA_LO - Memory Data Path Read Capture Low */ 2366 /*! @{ */ 2367 2368 #define DDRC_CAPTURE_DATA_LO_ECLD_MASK (0xFFFFFFFFU) 2369 #define DDRC_CAPTURE_DATA_LO_ECLD_SHIFT (0U) 2370 #define DDRC_CAPTURE_DATA_LO_ECLD_WIDTH (32U) 2371 #define DDRC_CAPTURE_DATA_LO_ECLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_DATA_LO_ECLD_SHIFT)) & DDRC_CAPTURE_DATA_LO_ECLD_MASK) 2372 /*! @} */ 2373 2374 /*! @name CAPTURE_ECC - Memory Data Path Read Capture ECC */ 2375 /*! @{ */ 2376 2377 #define DDRC_CAPTURE_ECC_ECE_MASK (0xFFFFFFFFU) 2378 #define DDRC_CAPTURE_ECC_ECE_SHIFT (0U) 2379 #define DDRC_CAPTURE_ECC_ECE_WIDTH (32U) 2380 #define DDRC_CAPTURE_ECC_ECE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ECC_ECE_SHIFT)) & DDRC_CAPTURE_ECC_ECE_MASK) 2381 /*! @} */ 2382 2383 /*! @name ERR_DETECT - Memory Error Detect */ 2384 /*! @{ */ 2385 2386 #define DDRC_ERR_DETECT_MSE_MASK (0x1U) 2387 #define DDRC_ERR_DETECT_MSE_SHIFT (0U) 2388 #define DDRC_ERR_DETECT_MSE_WIDTH (1U) 2389 #define DDRC_ERR_DETECT_MSE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MSE_SHIFT)) & DDRC_ERR_DETECT_MSE_MASK) 2390 2391 #define DDRC_ERR_DETECT_SBE_MASK (0x4U) 2392 #define DDRC_ERR_DETECT_SBE_SHIFT (2U) 2393 #define DDRC_ERR_DETECT_SBE_WIDTH (1U) 2394 #define DDRC_ERR_DETECT_SBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SBE_SHIFT)) & DDRC_ERR_DETECT_SBE_MASK) 2395 2396 #define DDRC_ERR_DETECT_MBE_MASK (0x8U) 2397 #define DDRC_ERR_DETECT_MBE_SHIFT (3U) 2398 #define DDRC_ERR_DETECT_MBE_WIDTH (1U) 2399 #define DDRC_ERR_DETECT_MBE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MBE_SHIFT)) & DDRC_ERR_DETECT_MBE_MASK) 2400 2401 #define DDRC_ERR_DETECT_REFRATEE_MASK (0x80U) 2402 #define DDRC_ERR_DETECT_REFRATEE_SHIFT (7U) 2403 #define DDRC_ERR_DETECT_REFRATEE_WIDTH (1U) 2404 #define DDRC_ERR_DETECT_REFRATEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_REFRATEE_SHIFT)) & DDRC_ERR_DETECT_REFRATEE_MASK) 2405 2406 #define DDRC_ERR_DETECT_LKSTP2E_MASK (0x100U) 2407 #define DDRC_ERR_DETECT_LKSTP2E_SHIFT (8U) 2408 #define DDRC_ERR_DETECT_LKSTP2E_WIDTH (1U) 2409 #define DDRC_ERR_DETECT_LKSTP2E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_LKSTP2E_SHIFT)) & DDRC_ERR_DETECT_LKSTP2E_MASK) 2410 2411 #define DDRC_ERR_DETECT_LKSTP1E_MASK (0x200U) 2412 #define DDRC_ERR_DETECT_LKSTP1E_SHIFT (9U) 2413 #define DDRC_ERR_DETECT_LKSTP1E_WIDTH (1U) 2414 #define DDRC_ERR_DETECT_LKSTP1E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_LKSTP1E_SHIFT)) & DDRC_ERR_DETECT_LKSTP1E_MASK) 2415 2416 #define DDRC_ERR_DETECT_PHYE_MASK (0x10000U) 2417 #define DDRC_ERR_DETECT_PHYE_SHIFT (16U) 2418 #define DDRC_ERR_DETECT_PHYE_WIDTH (1U) 2419 #define DDRC_ERR_DETECT_PHYE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_PHYE_SHIFT)) & DDRC_ERR_DETECT_PHYE_MASK) 2420 2421 #define DDRC_ERR_DETECT_IPE_MASK (0x80000U) 2422 #define DDRC_ERR_DETECT_IPE_SHIFT (19U) 2423 #define DDRC_ERR_DETECT_IPE_WIDTH (1U) 2424 #define DDRC_ERR_DETECT_IPE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_IPE_SHIFT)) & DDRC_ERR_DETECT_IPE_MASK) 2425 2426 #define DDRC_ERR_DETECT_UPDTMTE_MASK (0x100000U) 2427 #define DDRC_ERR_DETECT_UPDTMTE_SHIFT (20U) 2428 #define DDRC_ERR_DETECT_UPDTMTE_WIDTH (1U) 2429 #define DDRC_ERR_DETECT_UPDTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_UPDTMTE_SHIFT)) & DDRC_ERR_DETECT_UPDTMTE_MASK) 2430 2431 #define DDRC_ERR_DETECT_CRCE_MASK (0x200000U) 2432 #define DDRC_ERR_DETECT_CRCE_SHIFT (21U) 2433 #define DDRC_ERR_DETECT_CRCE_WIDTH (1U) 2434 #define DDRC_ERR_DETECT_CRCE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_CRCE_SHIFT)) & DDRC_ERR_DETECT_CRCE_MASK) 2435 2436 #define DDRC_ERR_DETECT_SMBE2_MASK (0x400000U) 2437 #define DDRC_ERR_DETECT_SMBE2_SHIFT (22U) 2438 #define DDRC_ERR_DETECT_SMBE2_WIDTH (1U) 2439 #define DDRC_ERR_DETECT_SMBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE2_SHIFT)) & DDRC_ERR_DETECT_SMBE2_MASK) 2440 2441 #define DDRC_ERR_DETECT_SMBE1_MASK (0x800000U) 2442 #define DDRC_ERR_DETECT_SMBE1_SHIFT (23U) 2443 #define DDRC_ERR_DETECT_SMBE1_WIDTH (1U) 2444 #define DDRC_ERR_DETECT_SMBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SMBE1_SHIFT)) & DDRC_ERR_DETECT_SMBE1_MASK) 2445 2446 #define DDRC_ERR_DETECT_SSBE2_MASK (0x1000000U) 2447 #define DDRC_ERR_DETECT_SSBE2_SHIFT (24U) 2448 #define DDRC_ERR_DETECT_SSBE2_WIDTH (1U) 2449 #define DDRC_ERR_DETECT_SSBE2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE2_SHIFT)) & DDRC_ERR_DETECT_SSBE2_MASK) 2450 2451 #define DDRC_ERR_DETECT_SSBE1_MASK (0x2000000U) 2452 #define DDRC_ERR_DETECT_SSBE1_SHIFT (25U) 2453 #define DDRC_ERR_DETECT_SSBE1_WIDTH (1U) 2454 #define DDRC_ERR_DETECT_SSBE1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_SSBE1_SHIFT)) & DDRC_ERR_DETECT_SSBE1_MASK) 2455 2456 #define DDRC_ERR_DETECT_WTAGE_MASK (0x4000000U) 2457 #define DDRC_ERR_DETECT_WTAGE_SHIFT (26U) 2458 #define DDRC_ERR_DETECT_WTAGE_WIDTH (1U) 2459 #define DDRC_ERR_DETECT_WTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_WTAGE_SHIFT)) & DDRC_ERR_DETECT_WTAGE_MASK) 2460 2461 #define DDRC_ERR_DETECT_RTAGE_MASK (0x8000000U) 2462 #define DDRC_ERR_DETECT_RTAGE_SHIFT (27U) 2463 #define DDRC_ERR_DETECT_RTAGE_WIDTH (1U) 2464 #define DDRC_ERR_DETECT_RTAGE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTAGE_SHIFT)) & DDRC_ERR_DETECT_RTAGE_MASK) 2465 2466 #define DDRC_ERR_DETECT_WTTE_MASK (0x10000000U) 2467 #define DDRC_ERR_DETECT_WTTE_SHIFT (28U) 2468 #define DDRC_ERR_DETECT_WTTE_WIDTH (1U) 2469 #define DDRC_ERR_DETECT_WTTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_WTTE_SHIFT)) & DDRC_ERR_DETECT_WTTE_MASK) 2470 2471 #define DDRC_ERR_DETECT_RTTE_MASK (0x20000000U) 2472 #define DDRC_ERR_DETECT_RTTE_SHIFT (29U) 2473 #define DDRC_ERR_DETECT_RTTE_WIDTH (1U) 2474 #define DDRC_ERR_DETECT_RTTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTTE_SHIFT)) & DDRC_ERR_DETECT_RTTE_MASK) 2475 2476 #define DDRC_ERR_DETECT_RTMTE_MASK (0x40000000U) 2477 #define DDRC_ERR_DETECT_RTMTE_SHIFT (30U) 2478 #define DDRC_ERR_DETECT_RTMTE_WIDTH (1U) 2479 #define DDRC_ERR_DETECT_RTMTE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_RTMTE_SHIFT)) & DDRC_ERR_DETECT_RTMTE_MASK) 2480 2481 #define DDRC_ERR_DETECT_MME_MASK (0x80000000U) 2482 #define DDRC_ERR_DETECT_MME_SHIFT (31U) 2483 #define DDRC_ERR_DETECT_MME_WIDTH (1U) 2484 #define DDRC_ERR_DETECT_MME(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DETECT_MME_SHIFT)) & DDRC_ERR_DETECT_MME_MASK) 2485 /*! @} */ 2486 2487 /*! @name ERR_DISABLE - Memory Error Disable */ 2488 /*! @{ */ 2489 2490 #define DDRC_ERR_DISABLE_MSED_MASK (0x1U) 2491 #define DDRC_ERR_DISABLE_MSED_SHIFT (0U) 2492 #define DDRC_ERR_DISABLE_MSED_WIDTH (1U) 2493 #define DDRC_ERR_DISABLE_MSED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MSED_SHIFT)) & DDRC_ERR_DISABLE_MSED_MASK) 2494 2495 #define DDRC_ERR_DISABLE_SBED_MASK (0x4U) 2496 #define DDRC_ERR_DISABLE_SBED_SHIFT (2U) 2497 #define DDRC_ERR_DISABLE_SBED_WIDTH (1U) 2498 #define DDRC_ERR_DISABLE_SBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_SBED_SHIFT)) & DDRC_ERR_DISABLE_SBED_MASK) 2499 2500 #define DDRC_ERR_DISABLE_MBED_MASK (0x8U) 2501 #define DDRC_ERR_DISABLE_MBED_SHIFT (3U) 2502 #define DDRC_ERR_DISABLE_MBED_WIDTH (1U) 2503 #define DDRC_ERR_DISABLE_MBED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_MBED_SHIFT)) & DDRC_ERR_DISABLE_MBED_MASK) 2504 2505 #define DDRC_ERR_DISABLE_REFRATEED_MASK (0x80U) 2506 #define DDRC_ERR_DISABLE_REFRATEED_SHIFT (7U) 2507 #define DDRC_ERR_DISABLE_REFRATEED_WIDTH (1U) 2508 #define DDRC_ERR_DISABLE_REFRATEED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_REFRATEED_SHIFT)) & DDRC_ERR_DISABLE_REFRATEED_MASK) 2509 2510 #define DDRC_ERR_DISABLE_PHYED_MASK (0x10000U) 2511 #define DDRC_ERR_DISABLE_PHYED_SHIFT (16U) 2512 #define DDRC_ERR_DISABLE_PHYED_WIDTH (1U) 2513 #define DDRC_ERR_DISABLE_PHYED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_PHYED_SHIFT)) & DDRC_ERR_DISABLE_PHYED_MASK) 2514 2515 #define DDRC_ERR_DISABLE_UPDTMTED_MASK (0x100000U) 2516 #define DDRC_ERR_DISABLE_UPDTMTED_SHIFT (20U) 2517 #define DDRC_ERR_DISABLE_UPDTMTED_WIDTH (1U) 2518 #define DDRC_ERR_DISABLE_UPDTMTED(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_DISABLE_UPDTMTED_SHIFT)) & DDRC_ERR_DISABLE_UPDTMTED_MASK) 2519 /*! @} */ 2520 2521 /*! @name ERR_INT_EN - Memory Error Interrupt Enable */ 2522 /*! @{ */ 2523 2524 #define DDRC_ERR_INT_EN_MSEE_MASK (0x1U) 2525 #define DDRC_ERR_INT_EN_MSEE_SHIFT (0U) 2526 #define DDRC_ERR_INT_EN_MSEE_WIDTH (1U) 2527 #define DDRC_ERR_INT_EN_MSEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MSEE_SHIFT)) & DDRC_ERR_INT_EN_MSEE_MASK) 2528 2529 #define DDRC_ERR_INT_EN_SBEE_MASK (0x4U) 2530 #define DDRC_ERR_INT_EN_SBEE_SHIFT (2U) 2531 #define DDRC_ERR_INT_EN_SBEE_WIDTH (1U) 2532 #define DDRC_ERR_INT_EN_SBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SBEE_SHIFT)) & DDRC_ERR_INT_EN_SBEE_MASK) 2533 2534 #define DDRC_ERR_INT_EN_MBEE_MASK (0x8U) 2535 #define DDRC_ERR_INT_EN_MBEE_SHIFT (3U) 2536 #define DDRC_ERR_INT_EN_MBEE_WIDTH (1U) 2537 #define DDRC_ERR_INT_EN_MBEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_MBEE_SHIFT)) & DDRC_ERR_INT_EN_MBEE_MASK) 2538 2539 #define DDRC_ERR_INT_EN_SSBE12E_MASK (0x10U) 2540 #define DDRC_ERR_INT_EN_SSBE12E_SHIFT (4U) 2541 #define DDRC_ERR_INT_EN_SSBE12E_WIDTH (1U) 2542 #define DDRC_ERR_INT_EN_SSBE12E(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_SSBE12E_SHIFT)) & DDRC_ERR_INT_EN_SSBE12E_MASK) 2543 2544 #define DDRC_ERR_INT_EN_REFRATEEE_MASK (0x80U) 2545 #define DDRC_ERR_INT_EN_REFRATEEE_SHIFT (7U) 2546 #define DDRC_ERR_INT_EN_REFRATEEE_WIDTH (1U) 2547 #define DDRC_ERR_INT_EN_REFRATEEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_REFRATEEE_SHIFT)) & DDRC_ERR_INT_EN_REFRATEEE_MASK) 2548 2549 #define DDRC_ERR_INT_EN_PHYEE_MASK (0x10000U) 2550 #define DDRC_ERR_INT_EN_PHYEE_SHIFT (16U) 2551 #define DDRC_ERR_INT_EN_PHYEE_WIDTH (1U) 2552 #define DDRC_ERR_INT_EN_PHYEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_PHYEE_SHIFT)) & DDRC_ERR_INT_EN_PHYEE_MASK) 2553 2554 #define DDRC_ERR_INT_EN_UPDTMTEE_MASK (0x100000U) 2555 #define DDRC_ERR_INT_EN_UPDTMTEE_SHIFT (20U) 2556 #define DDRC_ERR_INT_EN_UPDTMTEE_WIDTH (1U) 2557 #define DDRC_ERR_INT_EN_UPDTMTEE(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_INT_EN_UPDTMTEE_SHIFT)) & DDRC_ERR_INT_EN_UPDTMTEE_MASK) 2558 /*! @} */ 2559 2560 /*! @name CAPTURE_ATTRIBUTES - Memory Error Attributes Capture */ 2561 /*! @{ */ 2562 2563 #define DDRC_CAPTURE_ATTRIBUTES_VLD_MASK (0x1U) 2564 #define DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT (0U) 2565 #define DDRC_CAPTURE_ATTRIBUTES_VLD_WIDTH (1U) 2566 #define DDRC_CAPTURE_ATTRIBUTES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_VLD_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_VLD_MASK) 2567 2568 #define DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK (0x3000U) 2569 #define DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT (12U) 2570 #define DDRC_CAPTURE_ATTRIBUTES_TTYP_WIDTH (2U) 2571 #define DDRC_CAPTURE_ATTRIBUTES_TTYP(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_TTYP_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_TTYP_MASK) 2572 2573 #define DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK (0x70000000U) 2574 #define DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT (28U) 2575 #define DDRC_CAPTURE_ATTRIBUTES_BNUM_WIDTH (3U) 2576 #define DDRC_CAPTURE_ATTRIBUTES_BNUM(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ATTRIBUTES_BNUM_SHIFT)) & DDRC_CAPTURE_ATTRIBUTES_BNUM_MASK) 2577 /*! @} */ 2578 2579 /*! @name CAPTURE_ADDRESS - Memory Error Address Capture */ 2580 /*! @{ */ 2581 2582 #define DDRC_CAPTURE_ADDRESS_CADDR_MASK (0xFFFFFFFFU) 2583 #define DDRC_CAPTURE_ADDRESS_CADDR_SHIFT (0U) 2584 #define DDRC_CAPTURE_ADDRESS_CADDR_WIDTH (32U) 2585 #define DDRC_CAPTURE_ADDRESS_CADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_ADDRESS_CADDR_SHIFT)) & DDRC_CAPTURE_ADDRESS_CADDR_MASK) 2586 /*! @} */ 2587 2588 /*! @name CAPTURE_EXT_ADDRESS - Memory Error Extended Address Capture */ 2589 /*! @{ */ 2590 2591 #define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK (0xFFU) 2592 #define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT (0U) 2593 #define DDRC_CAPTURE_EXT_ADDRESS_CEADDR_WIDTH (8U) 2594 #define DDRC_CAPTURE_EXT_ADDRESS_CEADDR(x) (((uint32_t)(((uint32_t)(x)) << DDRC_CAPTURE_EXT_ADDRESS_CEADDR_SHIFT)) & DDRC_CAPTURE_EXT_ADDRESS_CEADDR_MASK) 2595 /*! @} */ 2596 2597 /*! @name ERR_SBE - Single-Bit ECC Memory Error Management */ 2598 /*! @{ */ 2599 2600 #define DDRC_ERR_SBE_SBEC_MASK (0xFFU) 2601 #define DDRC_ERR_SBE_SBEC_SHIFT (0U) 2602 #define DDRC_ERR_SBE_SBEC_WIDTH (8U) 2603 #define DDRC_ERR_SBE_SBEC(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBEC_SHIFT)) & DDRC_ERR_SBE_SBEC_MASK) 2604 2605 #define DDRC_ERR_SBE_SBET_MASK (0xFF0000U) 2606 #define DDRC_ERR_SBE_SBET_SHIFT (16U) 2607 #define DDRC_ERR_SBE_SBET_WIDTH (8U) 2608 #define DDRC_ERR_SBE_SBET(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ERR_SBE_SBET_SHIFT)) & DDRC_ERR_SBE_SBET_MASK) 2609 /*! @} */ 2610 2611 /*! @name REG_LKSTP_CNTL - Lockstep Register Control */ 2612 /*! @{ */ 2613 2614 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP2_MASK (0x1U) 2615 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP2_SHIFT (0U) 2616 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP2_WIDTH (1U) 2617 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_LKSTP_CNTL_CLR_LKSTP2_SHIFT)) & DDRC_REG_LKSTP_CNTL_CLR_LKSTP2_MASK) 2618 2619 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP1_MASK (0x2U) 2620 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP1_SHIFT (1U) 2621 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP1_WIDTH (1U) 2622 #define DDRC_REG_LKSTP_CNTL_CLR_LKSTP1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_LKSTP_CNTL_CLR_LKSTP1_SHIFT)) & DDRC_REG_LKSTP_CNTL_CLR_LKSTP1_MASK) 2623 /*! @} */ 2624 2625 /*! @name REG_CRC_GRP_1 - Register CRC Code For Group 1 */ 2626 /*! @{ */ 2627 2628 #define DDRC_REG_CRC_GRP_1_CRC_1_MASK (0xFFFFFFFFU) 2629 #define DDRC_REG_CRC_GRP_1_CRC_1_SHIFT (0U) 2630 #define DDRC_REG_CRC_GRP_1_CRC_1_WIDTH (32U) 2631 #define DDRC_REG_CRC_GRP_1_CRC_1(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_CRC_GRP_1_CRC_1_SHIFT)) & DDRC_REG_CRC_GRP_1_CRC_1_MASK) 2632 /*! @} */ 2633 2634 /*! @name REG_CRC_GRP_2 - Register CRC Code For Group 2 */ 2635 /*! @{ */ 2636 2637 #define DDRC_REG_CRC_GRP_2_CRC_2_MASK (0xFFFFFFFFU) 2638 #define DDRC_REG_CRC_GRP_2_CRC_2_SHIFT (0U) 2639 #define DDRC_REG_CRC_GRP_2_CRC_2_WIDTH (32U) 2640 #define DDRC_REG_CRC_GRP_2_CRC_2(x) (((uint32_t)(((uint32_t)(x)) << DDRC_REG_CRC_GRP_2_CRC_2_SHIFT)) & DDRC_REG_CRC_GRP_2_CRC_2_MASK) 2641 /*! @} */ 2642 2643 /*! @name ECC_REG_0 - ECC Region 0 Configuration */ 2644 /*! @{ */ 2645 2646 #define DDRC_ECC_REG_0_REG_0_EA_MASK (0xFFFU) 2647 #define DDRC_ECC_REG_0_REG_0_EA_SHIFT (0U) 2648 #define DDRC_ECC_REG_0_REG_0_EA_WIDTH (12U) 2649 #define DDRC_ECC_REG_0_REG_0_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EA_SHIFT)) & DDRC_ECC_REG_0_REG_0_EA_MASK) 2650 2651 #define DDRC_ECC_REG_0_REG_0_SA_MASK (0xFFF0000U) 2652 #define DDRC_ECC_REG_0_REG_0_SA_SHIFT (16U) 2653 #define DDRC_ECC_REG_0_REG_0_SA_WIDTH (12U) 2654 #define DDRC_ECC_REG_0_REG_0_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_SA_SHIFT)) & DDRC_ECC_REG_0_REG_0_SA_MASK) 2655 2656 #define DDRC_ECC_REG_0_REG_0_EN_MASK (0x80000000U) 2657 #define DDRC_ECC_REG_0_REG_0_EN_SHIFT (31U) 2658 #define DDRC_ECC_REG_0_REG_0_EN_WIDTH (1U) 2659 #define DDRC_ECC_REG_0_REG_0_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_0_REG_0_EN_SHIFT)) & DDRC_ECC_REG_0_REG_0_EN_MASK) 2660 /*! @} */ 2661 2662 /*! @name ECC_REG_1 - ECC Region 1 Configuration */ 2663 /*! @{ */ 2664 2665 #define DDRC_ECC_REG_1_REG_1_EA_MASK (0xFFFU) 2666 #define DDRC_ECC_REG_1_REG_1_EA_SHIFT (0U) 2667 #define DDRC_ECC_REG_1_REG_1_EA_WIDTH (12U) 2668 #define DDRC_ECC_REG_1_REG_1_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EA_SHIFT)) & DDRC_ECC_REG_1_REG_1_EA_MASK) 2669 2670 #define DDRC_ECC_REG_1_REG_1_SA_MASK (0xFFF0000U) 2671 #define DDRC_ECC_REG_1_REG_1_SA_SHIFT (16U) 2672 #define DDRC_ECC_REG_1_REG_1_SA_WIDTH (12U) 2673 #define DDRC_ECC_REG_1_REG_1_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_SA_SHIFT)) & DDRC_ECC_REG_1_REG_1_SA_MASK) 2674 2675 #define DDRC_ECC_REG_1_REG_1_EN_MASK (0x80000000U) 2676 #define DDRC_ECC_REG_1_REG_1_EN_SHIFT (31U) 2677 #define DDRC_ECC_REG_1_REG_1_EN_WIDTH (1U) 2678 #define DDRC_ECC_REG_1_REG_1_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_1_REG_1_EN_SHIFT)) & DDRC_ECC_REG_1_REG_1_EN_MASK) 2679 /*! @} */ 2680 2681 /*! @name ECC_REG_2 - ECC Region 2 Configuration */ 2682 /*! @{ */ 2683 2684 #define DDRC_ECC_REG_2_REG_2_EA_MASK (0xFFFU) 2685 #define DDRC_ECC_REG_2_REG_2_EA_SHIFT (0U) 2686 #define DDRC_ECC_REG_2_REG_2_EA_WIDTH (12U) 2687 #define DDRC_ECC_REG_2_REG_2_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EA_SHIFT)) & DDRC_ECC_REG_2_REG_2_EA_MASK) 2688 2689 #define DDRC_ECC_REG_2_REG_2_SA_MASK (0xFFF0000U) 2690 #define DDRC_ECC_REG_2_REG_2_SA_SHIFT (16U) 2691 #define DDRC_ECC_REG_2_REG_2_SA_WIDTH (12U) 2692 #define DDRC_ECC_REG_2_REG_2_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_SA_SHIFT)) & DDRC_ECC_REG_2_REG_2_SA_MASK) 2693 2694 #define DDRC_ECC_REG_2_REG_2_EN_MASK (0x80000000U) 2695 #define DDRC_ECC_REG_2_REG_2_EN_SHIFT (31U) 2696 #define DDRC_ECC_REG_2_REG_2_EN_WIDTH (1U) 2697 #define DDRC_ECC_REG_2_REG_2_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_2_REG_2_EN_SHIFT)) & DDRC_ECC_REG_2_REG_2_EN_MASK) 2698 /*! @} */ 2699 2700 /*! @name ECC_REG_3 - ECC Region 3 Configuration */ 2701 /*! @{ */ 2702 2703 #define DDRC_ECC_REG_3_REG_3_EA_MASK (0xFFFU) 2704 #define DDRC_ECC_REG_3_REG_3_EA_SHIFT (0U) 2705 #define DDRC_ECC_REG_3_REG_3_EA_WIDTH (12U) 2706 #define DDRC_ECC_REG_3_REG_3_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EA_SHIFT)) & DDRC_ECC_REG_3_REG_3_EA_MASK) 2707 2708 #define DDRC_ECC_REG_3_REG_3_SA_MASK (0xFFF0000U) 2709 #define DDRC_ECC_REG_3_REG_3_SA_SHIFT (16U) 2710 #define DDRC_ECC_REG_3_REG_3_SA_WIDTH (12U) 2711 #define DDRC_ECC_REG_3_REG_3_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_SA_SHIFT)) & DDRC_ECC_REG_3_REG_3_SA_MASK) 2712 2713 #define DDRC_ECC_REG_3_REG_3_EN_MASK (0x80000000U) 2714 #define DDRC_ECC_REG_3_REG_3_EN_SHIFT (31U) 2715 #define DDRC_ECC_REG_3_REG_3_EN_WIDTH (1U) 2716 #define DDRC_ECC_REG_3_REG_3_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_3_REG_3_EN_SHIFT)) & DDRC_ECC_REG_3_REG_3_EN_MASK) 2717 /*! @} */ 2718 2719 /*! @name ECC_REG_4 - ECC Region 4 Configuration */ 2720 /*! @{ */ 2721 2722 #define DDRC_ECC_REG_4_REG_4_EA_MASK (0xFFFU) 2723 #define DDRC_ECC_REG_4_REG_4_EA_SHIFT (0U) 2724 #define DDRC_ECC_REG_4_REG_4_EA_WIDTH (12U) 2725 #define DDRC_ECC_REG_4_REG_4_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EA_SHIFT)) & DDRC_ECC_REG_4_REG_4_EA_MASK) 2726 2727 #define DDRC_ECC_REG_4_REG_4_SA_MASK (0xFFF0000U) 2728 #define DDRC_ECC_REG_4_REG_4_SA_SHIFT (16U) 2729 #define DDRC_ECC_REG_4_REG_4_SA_WIDTH (12U) 2730 #define DDRC_ECC_REG_4_REG_4_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_SA_SHIFT)) & DDRC_ECC_REG_4_REG_4_SA_MASK) 2731 2732 #define DDRC_ECC_REG_4_REG_4_EN_MASK (0x80000000U) 2733 #define DDRC_ECC_REG_4_REG_4_EN_SHIFT (31U) 2734 #define DDRC_ECC_REG_4_REG_4_EN_WIDTH (1U) 2735 #define DDRC_ECC_REG_4_REG_4_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_4_REG_4_EN_SHIFT)) & DDRC_ECC_REG_4_REG_4_EN_MASK) 2736 /*! @} */ 2737 2738 /*! @name ECC_REG_5 - ECC Region 5 Configuration */ 2739 /*! @{ */ 2740 2741 #define DDRC_ECC_REG_5_REG_5_EA_MASK (0xFFFU) 2742 #define DDRC_ECC_REG_5_REG_5_EA_SHIFT (0U) 2743 #define DDRC_ECC_REG_5_REG_5_EA_WIDTH (12U) 2744 #define DDRC_ECC_REG_5_REG_5_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EA_SHIFT)) & DDRC_ECC_REG_5_REG_5_EA_MASK) 2745 2746 #define DDRC_ECC_REG_5_REG_5_SA_MASK (0xFFF0000U) 2747 #define DDRC_ECC_REG_5_REG_5_SA_SHIFT (16U) 2748 #define DDRC_ECC_REG_5_REG_5_SA_WIDTH (12U) 2749 #define DDRC_ECC_REG_5_REG_5_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_SA_SHIFT)) & DDRC_ECC_REG_5_REG_5_SA_MASK) 2750 2751 #define DDRC_ECC_REG_5_REG_5_EN_MASK (0x80000000U) 2752 #define DDRC_ECC_REG_5_REG_5_EN_SHIFT (31U) 2753 #define DDRC_ECC_REG_5_REG_5_EN_WIDTH (1U) 2754 #define DDRC_ECC_REG_5_REG_5_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_5_REG_5_EN_SHIFT)) & DDRC_ECC_REG_5_REG_5_EN_MASK) 2755 /*! @} */ 2756 2757 /*! @name ECC_REG_6 - ECC Region 6 Configuration */ 2758 /*! @{ */ 2759 2760 #define DDRC_ECC_REG_6_REG_6_EA_MASK (0xFFFU) 2761 #define DDRC_ECC_REG_6_REG_6_EA_SHIFT (0U) 2762 #define DDRC_ECC_REG_6_REG_6_EA_WIDTH (12U) 2763 #define DDRC_ECC_REG_6_REG_6_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EA_SHIFT)) & DDRC_ECC_REG_6_REG_6_EA_MASK) 2764 2765 #define DDRC_ECC_REG_6_REG_6_SA_MASK (0xFFF0000U) 2766 #define DDRC_ECC_REG_6_REG_6_SA_SHIFT (16U) 2767 #define DDRC_ECC_REG_6_REG_6_SA_WIDTH (12U) 2768 #define DDRC_ECC_REG_6_REG_6_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_SA_SHIFT)) & DDRC_ECC_REG_6_REG_6_SA_MASK) 2769 2770 #define DDRC_ECC_REG_6_REG_6_EN_MASK (0x80000000U) 2771 #define DDRC_ECC_REG_6_REG_6_EN_SHIFT (31U) 2772 #define DDRC_ECC_REG_6_REG_6_EN_WIDTH (1U) 2773 #define DDRC_ECC_REG_6_REG_6_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_6_REG_6_EN_SHIFT)) & DDRC_ECC_REG_6_REG_6_EN_MASK) 2774 /*! @} */ 2775 2776 /*! @name ECC_REG_7 - ECC Region 7 Configuration */ 2777 /*! @{ */ 2778 2779 #define DDRC_ECC_REG_7_REG_7_EA_MASK (0xFFFU) 2780 #define DDRC_ECC_REG_7_REG_7_EA_SHIFT (0U) 2781 #define DDRC_ECC_REG_7_REG_7_EA_WIDTH (12U) 2782 #define DDRC_ECC_REG_7_REG_7_EA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EA_SHIFT)) & DDRC_ECC_REG_7_REG_7_EA_MASK) 2783 2784 #define DDRC_ECC_REG_7_REG_7_SA_MASK (0xFFF0000U) 2785 #define DDRC_ECC_REG_7_REG_7_SA_SHIFT (16U) 2786 #define DDRC_ECC_REG_7_REG_7_SA_WIDTH (12U) 2787 #define DDRC_ECC_REG_7_REG_7_SA(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_SA_SHIFT)) & DDRC_ECC_REG_7_REG_7_SA_MASK) 2788 2789 #define DDRC_ECC_REG_7_REG_7_EN_MASK (0x80000000U) 2790 #define DDRC_ECC_REG_7_REG_7_EN_SHIFT (31U) 2791 #define DDRC_ECC_REG_7_REG_7_EN_WIDTH (1U) 2792 #define DDRC_ECC_REG_7_REG_7_EN(x) (((uint32_t)(((uint32_t)(x)) << DDRC_ECC_REG_7_REG_7_EN_SHIFT)) & DDRC_ECC_REG_7_REG_7_EN_MASK) 2793 /*! @} */ 2794 2795 /*! 2796 * @} 2797 */ /* end of group DDRC_Register_Masks */ 2798 2799 /*! 2800 * @} 2801 */ /* end of group DDRC_Peripheral_Access_Layer */ 2802 2803 #endif /* #if !defined(S32Z2_DDRC_H_) */ 2804
