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Searched refs:DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (Results 1 – 25 of 34) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h12729 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12735 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h12727 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12733 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h12727 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12733 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h12729 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12735 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h12729 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12735 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h12727 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12733 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
DMIMX8MN6_ca53.h12756 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12762 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h16031 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
16037 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h16031 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
16037 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h16031 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
16037 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h16031 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
16037 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h16031 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
16037 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
DMIMX8MM6_ca53.h12574 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12580 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h12550 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12556 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX2/
DMIMX8QX2_cm4.h12068 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12074 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX1/
DMIMX8QX1_cm4.h12068 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12074 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX1/
DMIMX8DX1_cm4.h12068 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12074 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX2/
DMIMX8DX2_cm4.h12068 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12074 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8QX3/
DMIMX8QX3_cm4.h12066 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12072 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8DX4/
DMIMX8DX4_cm4.h12066 #define DDRC_PCFGWQOS0_0_wqos_map_region0_MASK (0x30000U) macro
12072 …int32_t)(x)) << DDRC_PCFGWQOS0_0_wqos_map_region0_SHIFT)) & DDRC_PCFGWQOS0_0_wqos_map_region0_MASK)

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