1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DCU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DCU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DCU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DCU_Peripheral_Access_Layer DCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DCU - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t OCM_PADD1; /**< OCM PADD1 Register, offset: 0x0 */ 74 __IO uint32_t OCM_PADD2; /**< OCM PADD2 Register, offset: 0x4 */ 75 uint8_t RESERVED_0[8]; 76 __IO uint32_t OCM_PCOUNT1; /**< OCM PCOUNT1 Register, offset: 0x10 */ 77 __IO uint32_t OCM_PCOUNT2; /**< OCM PCOUNT2 Register, offset: 0x14 */ 78 uint8_t RESERVED_1[8]; 79 __I uint32_t CEVAX_A_PC; /**< CEVAX A PC Register, offset: 0x20 */ 80 __IO uint32_t OCM_DADD_LOW; /**< OCM DDD Low Register, offset: 0x24 */ 81 __IO uint32_t OCM_DADD_HIGH; /**< OCM DADD HIGH Register, offset: 0x28 */ 82 uint8_t RESERVED_2[4]; 83 __IO uint32_t OCM_ACOUNT; /**< OCM ACOUNT Register, offset: 0x30 */ 84 __IO uint32_t OCM_DCOUNT; /**< OCM DCOUNT Register, offset: 0x34 */ 85 __IO uint32_t OCM_DVM; /**< OCM DVM Register, offset: 0x38 */ 86 uint8_t RESERVED_3[4]; 87 __IO uint32_t OCM_CONTROL; /**< OCM CONTROL Register, offset: 0x40 */ 88 __IO uint32_t OCM_SA_BP_EN; /**< OCM SA BP EN Register, offset: 0x44 */ 89 __I uint32_t MEM_CONFIG; /**< MEM CONFIG Register, offset: 0x48 */ 90 __I uint32_t MSS_CONFIG; /**< MSS CONFIG Register, offset: 0x4C */ 91 __I uint32_t OCM_STATUS; /**< OCM STATUS Register, offset: 0x50 */ 92 __I uint32_t OCM_SA_BP_ST; /**< OCM SA BP ST Register, offset: 0x54 */ 93 __I uint32_t M_CONFIG; /**< M CONFIG Register, offset: 0x58 */ 94 __I uint32_t S_CONFIG; /**< S_CONFIG Register, offset: 0x5C */ 95 __I uint32_t DEBUG_CONFIG; /**< DEBUG CONFIG Register, offset: 0x60 */ 96 __I uint32_t CORE_VERSION; /**< CORE VERSION Register, offset: 0x64 */ 97 __I uint32_t CORE_ID; /**< CORE ID Register, offset: 0x68 */ 98 __I uint32_t CORE_CONFIG; /**< CORE CONFIG Register, offset: 0x6C */ 99 } DCU_Type, *DCU_MemMapPtr; 100 101 /** Number of instances of the DCU module. */ 102 #define DCU_INSTANCE_COUNT (1u) 103 104 /* DCU - Peripheral instance base addresses */ 105 /** Peripheral CEVA_SPF2__DCU base address */ 106 #define IP_CEVA_SPF2__DCU_BASE (0x24400110u) 107 /** Peripheral CEVA_SPF2__DCU base pointer */ 108 #define IP_CEVA_SPF2__DCU ((DCU_Type *)IP_CEVA_SPF2__DCU_BASE) 109 /** Array initializer of DCU peripheral base addresses */ 110 #define IP_DCU_BASE_ADDRS { IP_CEVA_SPF2__DCU_BASE } 111 /** Array initializer of DCU peripheral base pointers */ 112 #define IP_DCU_BASE_PTRS { IP_CEVA_SPF2__DCU } 113 114 /* ---------------------------------------------------------------------------- 115 -- DCU Register Masks 116 ---------------------------------------------------------------------------- */ 117 118 /*! 119 * @addtogroup DCU_Register_Masks DCU Register Masks 120 * @{ 121 */ 122 123 /*! @name OCM_PADD1 - OCM PADD1 Register */ 124 /*! @{ */ 125 126 #define DCU_OCM_PADD1_OCM_PADD1_MASK (0xFFFFFFFFU) 127 #define DCU_OCM_PADD1_OCM_PADD1_SHIFT (0U) 128 #define DCU_OCM_PADD1_OCM_PADD1_WIDTH (32U) 129 #define DCU_OCM_PADD1_OCM_PADD1(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_PADD1_OCM_PADD1_SHIFT)) & DCU_OCM_PADD1_OCM_PADD1_MASK) 130 /*! @} */ 131 132 /*! @name OCM_PADD2 - OCM PADD2 Register */ 133 /*! @{ */ 134 135 #define DCU_OCM_PADD2_OCM_PADD2_MASK (0xFFFFFFFFU) 136 #define DCU_OCM_PADD2_OCM_PADD2_SHIFT (0U) 137 #define DCU_OCM_PADD2_OCM_PADD2_WIDTH (32U) 138 #define DCU_OCM_PADD2_OCM_PADD2(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_PADD2_OCM_PADD2_SHIFT)) & DCU_OCM_PADD2_OCM_PADD2_MASK) 139 /*! @} */ 140 141 /*! @name OCM_PCOUNT1 - OCM PCOUNT1 Register */ 142 /*! @{ */ 143 144 #define DCU_OCM_PCOUNT1_OCM_PCOUNT1_MASK (0xFFFFU) 145 #define DCU_OCM_PCOUNT1_OCM_PCOUNT1_SHIFT (0U) 146 #define DCU_OCM_PCOUNT1_OCM_PCOUNT1_WIDTH (16U) 147 #define DCU_OCM_PCOUNT1_OCM_PCOUNT1(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_PCOUNT1_OCM_PCOUNT1_SHIFT)) & DCU_OCM_PCOUNT1_OCM_PCOUNT1_MASK) 148 /*! @} */ 149 150 /*! @name OCM_PCOUNT2 - OCM PCOUNT2 Register */ 151 /*! @{ */ 152 153 #define DCU_OCM_PCOUNT2_OCM_PCOUNT2_MASK (0xFFFFU) 154 #define DCU_OCM_PCOUNT2_OCM_PCOUNT2_SHIFT (0U) 155 #define DCU_OCM_PCOUNT2_OCM_PCOUNT2_WIDTH (16U) 156 #define DCU_OCM_PCOUNT2_OCM_PCOUNT2(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_PCOUNT2_OCM_PCOUNT2_SHIFT)) & DCU_OCM_PCOUNT2_OCM_PCOUNT2_MASK) 157 /*! @} */ 158 159 /*! @name CEVAX_A_PC - CEVAX A PC Register */ 160 /*! @{ */ 161 162 #define DCU_CEVAX_A_PC_CEVAX_A_PC_MASK (0xFFFFFFFFU) 163 #define DCU_CEVAX_A_PC_CEVAX_A_PC_SHIFT (0U) 164 #define DCU_CEVAX_A_PC_CEVAX_A_PC_WIDTH (32U) 165 #define DCU_CEVAX_A_PC_CEVAX_A_PC(x) (((uint32_t)(((uint32_t)(x)) << DCU_CEVAX_A_PC_CEVAX_A_PC_SHIFT)) & DCU_CEVAX_A_PC_CEVAX_A_PC_MASK) 166 /*! @} */ 167 168 /*! @name OCM_DADD_LOW - OCM DDD Low Register */ 169 /*! @{ */ 170 171 #define DCU_OCM_DADD_LOW_OCM_DADD_LOW_MASK (0xFFFFFFFFU) 172 #define DCU_OCM_DADD_LOW_OCM_DADD_LOW_SHIFT (0U) 173 #define DCU_OCM_DADD_LOW_OCM_DADD_LOW_WIDTH (32U) 174 #define DCU_OCM_DADD_LOW_OCM_DADD_LOW(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_DADD_LOW_OCM_DADD_LOW_SHIFT)) & DCU_OCM_DADD_LOW_OCM_DADD_LOW_MASK) 175 /*! @} */ 176 177 /*! @name OCM_DADD_HIGH - OCM DADD HIGH Register */ 178 /*! @{ */ 179 180 #define DCU_OCM_DADD_HIGH_OCM_DADD_HIGH_MASK (0xFFFFFFFFU) 181 #define DCU_OCM_DADD_HIGH_OCM_DADD_HIGH_SHIFT (0U) 182 #define DCU_OCM_DADD_HIGH_OCM_DADD_HIGH_WIDTH (32U) 183 #define DCU_OCM_DADD_HIGH_OCM_DADD_HIGH(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_DADD_HIGH_OCM_DADD_HIGH_SHIFT)) & DCU_OCM_DADD_HIGH_OCM_DADD_HIGH_MASK) 184 /*! @} */ 185 186 /*! @name OCM_ACOUNT - OCM ACOUNT Register */ 187 /*! @{ */ 188 189 #define DCU_OCM_ACOUNT_OCM_ACOUNT_MASK (0xFFFFU) 190 #define DCU_OCM_ACOUNT_OCM_ACOUNT_SHIFT (0U) 191 #define DCU_OCM_ACOUNT_OCM_ACOUNT_WIDTH (16U) 192 #define DCU_OCM_ACOUNT_OCM_ACOUNT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_ACOUNT_OCM_ACOUNT_SHIFT)) & DCU_OCM_ACOUNT_OCM_ACOUNT_MASK) 193 /*! @} */ 194 195 /*! @name OCM_DCOUNT - OCM DCOUNT Register */ 196 /*! @{ */ 197 198 #define DCU_OCM_DCOUNT_OCM_DCOUNT_MASK (0xFFFFU) 199 #define DCU_OCM_DCOUNT_OCM_DCOUNT_SHIFT (0U) 200 #define DCU_OCM_DCOUNT_OCM_DCOUNT_WIDTH (16U) 201 #define DCU_OCM_DCOUNT_OCM_DCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_DCOUNT_OCM_DCOUNT_SHIFT)) & DCU_OCM_DCOUNT_OCM_DCOUNT_MASK) 202 /*! @} */ 203 204 /*! @name OCM_DVM - OCM DVM Register */ 205 /*! @{ */ 206 207 #define DCU_OCM_DVM_OCM_DVM_MASK (0xFFFFFFFFU) 208 #define DCU_OCM_DVM_OCM_DVM_SHIFT (0U) 209 #define DCU_OCM_DVM_OCM_DVM_WIDTH (32U) 210 #define DCU_OCM_DVM_OCM_DVM(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_DVM_OCM_DVM_SHIFT)) & DCU_OCM_DVM_OCM_DVM_MASK) 211 /*! @} */ 212 213 /*! @name OCM_CONTROL - OCM CONTROL Register */ 214 /*! @{ */ 215 216 #define DCU_OCM_CONTROL_DEBUG_ENABLE_MASK (0x1U) 217 #define DCU_OCM_CONTROL_DEBUG_ENABLE_SHIFT (0U) 218 #define DCU_OCM_CONTROL_DEBUG_ENABLE_WIDTH (1U) 219 #define DCU_OCM_CONTROL_DEBUG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_DEBUG_ENABLE_SHIFT)) & DCU_OCM_CONTROL_DEBUG_ENABLE_MASK) 220 221 #define DCU_OCM_CONTROL_BP_DETECT_EN_MASK (0x2U) 222 #define DCU_OCM_CONTROL_BP_DETECT_EN_SHIFT (1U) 223 #define DCU_OCM_CONTROL_BP_DETECT_EN_WIDTH (1U) 224 #define DCU_OCM_CONTROL_BP_DETECT_EN(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_BP_DETECT_EN_SHIFT)) & DCU_OCM_CONTROL_BP_DETECT_EN_MASK) 225 226 #define DCU_OCM_CONTROL_CORE_RST_MASK (0x4U) 227 #define DCU_OCM_CONTROL_CORE_RST_SHIFT (2U) 228 #define DCU_OCM_CONTROL_CORE_RST_WIDTH (1U) 229 #define DCU_OCM_CONTROL_CORE_RST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_CORE_RST_SHIFT)) & DCU_OCM_CONTROL_CORE_RST_MASK) 230 231 #define DCU_OCM_CONTROL_MSS_RST_MASK (0x8U) 232 #define DCU_OCM_CONTROL_MSS_RST_SHIFT (3U) 233 #define DCU_OCM_CONTROL_MSS_RST_WIDTH (1U) 234 #define DCU_OCM_CONTROL_MSS_RST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_MSS_RST_SHIFT)) & DCU_OCM_CONTROL_MSS_RST_MASK) 235 236 #define DCU_OCM_CONTROL_TRAPE_EN_MASK (0x10U) 237 #define DCU_OCM_CONTROL_TRAPE_EN_SHIFT (4U) 238 #define DCU_OCM_CONTROL_TRAPE_EN_WIDTH (1U) 239 #define DCU_OCM_CONTROL_TRAPE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_TRAPE_EN_SHIFT)) & DCU_OCM_CONTROL_TRAPE_EN_MASK) 240 241 #define DCU_OCM_CONTROL_STOP_MASK (0x20U) 242 #define DCU_OCM_CONTROL_STOP_SHIFT (5U) 243 #define DCU_OCM_CONTROL_STOP_WIDTH (1U) 244 #define DCU_OCM_CONTROL_STOP(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_STOP_SHIFT)) & DCU_OCM_CONTROL_STOP_MASK) 245 246 #define DCU_OCM_CONTROL_STEP_MASK (0x40U) 247 #define DCU_OCM_CONTROL_STEP_SHIFT (6U) 248 #define DCU_OCM_CONTROL_STEP_WIDTH (1U) 249 #define DCU_OCM_CONTROL_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_STEP_SHIFT)) & DCU_OCM_CONTROL_STEP_MASK) 250 251 #define DCU_OCM_CONTROL_PADD_INC_MASK (0x80U) 252 #define DCU_OCM_CONTROL_PADD_INC_SHIFT (7U) 253 #define DCU_OCM_CONTROL_PADD_INC_WIDTH (1U) 254 #define DCU_OCM_CONTROL_PADD_INC(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_PADD_INC_SHIFT)) & DCU_OCM_CONTROL_PADD_INC_MASK) 255 256 #define DCU_OCM_CONTROL_NIDIS_MASK (0x100U) 257 #define DCU_OCM_CONTROL_NIDIS_SHIFT (8U) 258 #define DCU_OCM_CONTROL_NIDIS_WIDTH (1U) 259 #define DCU_OCM_CONTROL_NIDIS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_NIDIS_SHIFT)) & DCU_OCM_CONTROL_NIDIS_MASK) 260 261 #define DCU_OCM_CONTROL_CIDIS_MASK (0x200U) 262 #define DCU_OCM_CONTROL_CIDIS_SHIFT (9U) 263 #define DCU_OCM_CONTROL_CIDIS_WIDTH (1U) 264 #define DCU_OCM_CONTROL_CIDIS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_CIDIS_SHIFT)) & DCU_OCM_CONTROL_CIDIS_MASK) 265 266 #define DCU_OCM_CONTROL_TINIS_MASK (0x400U) 267 #define DCU_OCM_CONTROL_TINIS_SHIFT (10U) 268 #define DCU_OCM_CONTROL_TINIS_WIDTH (1U) 269 #define DCU_OCM_CONTROL_TINIS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_TINIS_SHIFT)) & DCU_OCM_CONTROL_TINIS_MASK) 270 271 #define DCU_OCM_CONTROL_GP_OUT_MASK (0xF000U) 272 #define DCU_OCM_CONTROL_GP_OUT_SHIFT (12U) 273 #define DCU_OCM_CONTROL_GP_OUT_WIDTH (4U) 274 #define DCU_OCM_CONTROL_GP_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_GP_OUT_SHIFT)) & DCU_OCM_CONTROL_GP_OUT_MASK) 275 276 #define DCU_OCM_CONTROL_DVM_TYPE_MASK (0x30000U) 277 #define DCU_OCM_CONTROL_DVM_TYPE_SHIFT (16U) 278 #define DCU_OCM_CONTROL_DVM_TYPE_WIDTH (2U) 279 #define DCU_OCM_CONTROL_DVM_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_DVM_TYPE_SHIFT)) & DCU_OCM_CONTROL_DVM_TYPE_MASK) 280 281 #define DCU_OCM_CONTROL_RST_STATUS_MASK (0x100000U) 282 #define DCU_OCM_CONTROL_RST_STATUS_SHIFT (20U) 283 #define DCU_OCM_CONTROL_RST_STATUS_WIDTH (1U) 284 #define DCU_OCM_CONTROL_RST_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_RST_STATUS_SHIFT)) & DCU_OCM_CONTROL_RST_STATUS_MASK) 285 286 #define DCU_OCM_CONTROL_AUTO_CLK_MASK (0x200000U) 287 #define DCU_OCM_CONTROL_AUTO_CLK_SHIFT (21U) 288 #define DCU_OCM_CONTROL_AUTO_CLK_WIDTH (1U) 289 #define DCU_OCM_CONTROL_AUTO_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_AUTO_CLK_SHIFT)) & DCU_OCM_CONTROL_AUTO_CLK_MASK) 290 291 #define DCU_OCM_CONTROL_BOOT_MASK_MASK (0x800000U) 292 #define DCU_OCM_CONTROL_BOOT_MASK_SHIFT (23U) 293 #define DCU_OCM_CONTROL_BOOT_MASK_WIDTH (1U) 294 #define DCU_OCM_CONTROL_BOOT_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_BOOT_MASK_SHIFT)) & DCU_OCM_CONTROL_BOOT_MASK_MASK) 295 296 #define DCU_OCM_CONTROL_APB_ERROR_MASK (0x1000000U) 297 #define DCU_OCM_CONTROL_APB_ERROR_SHIFT (24U) 298 #define DCU_OCM_CONTROL_APB_ERROR_WIDTH (1U) 299 #define DCU_OCM_CONTROL_APB_ERROR(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_CONTROL_APB_ERROR_SHIFT)) & DCU_OCM_CONTROL_APB_ERROR_MASK) 300 /*! @} */ 301 302 /*! @name OCM_SA_BP_EN - OCM SA BP EN Register */ 303 /*! @{ */ 304 305 #define DCU_OCM_SA_BP_EN_SA_EXT_MASK (0x3U) 306 #define DCU_OCM_SA_BP_EN_SA_EXT_SHIFT (0U) 307 #define DCU_OCM_SA_BP_EN_SA_EXT_WIDTH (2U) 308 #define DCU_OCM_SA_BP_EN_SA_EXT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_EXT_SHIFT)) & DCU_OCM_SA_BP_EN_SA_EXT_MASK) 309 310 #define DCU_OCM_SA_BP_EN_DMA_DA_E_MASK (0x8U) 311 #define DCU_OCM_SA_BP_EN_DMA_DA_E_SHIFT (3U) 312 #define DCU_OCM_SA_BP_EN_DMA_DA_E_WIDTH (1U) 313 #define DCU_OCM_SA_BP_EN_DMA_DA_E(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_DMA_DA_E_SHIFT)) & DCU_OCM_SA_BP_EN_DMA_DA_E_MASK) 314 315 #define DCU_OCM_SA_BP_EN_SA_PA_MASK (0x30U) 316 #define DCU_OCM_SA_BP_EN_SA_PA_SHIFT (4U) 317 #define DCU_OCM_SA_BP_EN_SA_PA_WIDTH (2U) 318 #define DCU_OCM_SA_BP_EN_SA_PA(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_PA_SHIFT)) & DCU_OCM_SA_BP_EN_SA_PA_MASK) 319 320 #define DCU_OCM_SA_BP_EN_SA_DA_RD_MASK (0x100U) 321 #define DCU_OCM_SA_BP_EN_SA_DA_RD_SHIFT (8U) 322 #define DCU_OCM_SA_BP_EN_SA_DA_RD_WIDTH (1U) 323 #define DCU_OCM_SA_BP_EN_SA_DA_RD(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_DA_RD_SHIFT)) & DCU_OCM_SA_BP_EN_SA_DA_RD_MASK) 324 325 #define DCU_OCM_SA_BP_EN_SA_DA_WR_MASK (0x1000U) 326 #define DCU_OCM_SA_BP_EN_SA_DA_WR_SHIFT (12U) 327 #define DCU_OCM_SA_BP_EN_SA_DA_WR_WIDTH (1U) 328 #define DCU_OCM_SA_BP_EN_SA_DA_WR(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_DA_WR_SHIFT)) & DCU_OCM_SA_BP_EN_SA_DA_WR_MASK) 329 330 #define DCU_OCM_SA_BP_EN_CO_A_EN_MASK (0x2000U) 331 #define DCU_OCM_SA_BP_EN_CO_A_EN_SHIFT (13U) 332 #define DCU_OCM_SA_BP_EN_CO_A_EN_WIDTH (1U) 333 #define DCU_OCM_SA_BP_EN_CO_A_EN(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_CO_A_EN_SHIFT)) & DCU_OCM_SA_BP_EN_CO_A_EN_MASK) 334 335 #define DCU_OCM_SA_BP_EN_CO_D_EN_MASK (0x4000U) 336 #define DCU_OCM_SA_BP_EN_CO_D_EN_SHIFT (14U) 337 #define DCU_OCM_SA_BP_EN_CO_D_EN_WIDTH (1U) 338 #define DCU_OCM_SA_BP_EN_CO_D_EN(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_CO_D_EN_SHIFT)) & DCU_OCM_SA_BP_EN_CO_D_EN_MASK) 339 340 #define DCU_OCM_SA_BP_EN_SA_DVM_MASK (0x20000U) 341 #define DCU_OCM_SA_BP_EN_SA_DVM_SHIFT (17U) 342 #define DCU_OCM_SA_BP_EN_SA_DVM_WIDTH (1U) 343 #define DCU_OCM_SA_BP_EN_SA_DVM(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_DVM_SHIFT)) & DCU_OCM_SA_BP_EN_SA_DVM_MASK) 344 345 #define DCU_OCM_SA_BP_EN_SA_COMB_RD_MASK (0x40000U) 346 #define DCU_OCM_SA_BP_EN_SA_COMB_RD_SHIFT (18U) 347 #define DCU_OCM_SA_BP_EN_SA_COMB_RD_WIDTH (1U) 348 #define DCU_OCM_SA_BP_EN_SA_COMB_RD(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_COMB_RD_SHIFT)) & DCU_OCM_SA_BP_EN_SA_COMB_RD_MASK) 349 350 #define DCU_OCM_SA_BP_EN_SA_COMB_WR_MASK (0x80000U) 351 #define DCU_OCM_SA_BP_EN_SA_COMB_WR_SHIFT (19U) 352 #define DCU_OCM_SA_BP_EN_SA_COMB_WR_WIDTH (1U) 353 #define DCU_OCM_SA_BP_EN_SA_COMB_WR(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_EN_SA_COMB_WR_SHIFT)) & DCU_OCM_SA_BP_EN_SA_COMB_WR_MASK) 354 /*! @} */ 355 356 /*! @name MEM_CONFIG - MEM CONFIG Register */ 357 /*! @{ */ 358 359 #define DCU_MEM_CONFIG_PMEM_TCM_SIZE_MASK (0xF0U) 360 #define DCU_MEM_CONFIG_PMEM_TCM_SIZE_SHIFT (4U) 361 #define DCU_MEM_CONFIG_PMEM_TCM_SIZE_WIDTH (4U) 362 #define DCU_MEM_CONFIG_PMEM_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_PMEM_TCM_SIZE_SHIFT)) & DCU_MEM_CONFIG_PMEM_TCM_SIZE_MASK) 363 364 #define DCU_MEM_CONFIG_PMEM_CAC_SIZE_MASK (0xF00U) 365 #define DCU_MEM_CONFIG_PMEM_CAC_SIZE_SHIFT (8U) 366 #define DCU_MEM_CONFIG_PMEM_CAC_SIZE_WIDTH (4U) 367 #define DCU_MEM_CONFIG_PMEM_CAC_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_PMEM_CAC_SIZE_SHIFT)) & DCU_MEM_CONFIG_PMEM_CAC_SIZE_MASK) 368 369 #define DCU_MEM_CONFIG_PMEM_CAC_WAY_MASK (0x1000U) 370 #define DCU_MEM_CONFIG_PMEM_CAC_WAY_SHIFT (12U) 371 #define DCU_MEM_CONFIG_PMEM_CAC_WAY_WIDTH (1U) 372 #define DCU_MEM_CONFIG_PMEM_CAC_WAY(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_PMEM_CAC_WAY_SHIFT)) & DCU_MEM_CONFIG_PMEM_CAC_WAY_MASK) 373 374 #define DCU_MEM_CONFIG_DMEM_TCM_SIZE_MASK (0xF0000U) 375 #define DCU_MEM_CONFIG_DMEM_TCM_SIZE_SHIFT (16U) 376 #define DCU_MEM_CONFIG_DMEM_TCM_SIZE_WIDTH (4U) 377 #define DCU_MEM_CONFIG_DMEM_TCM_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_DMEM_TCM_SIZE_SHIFT)) & DCU_MEM_CONFIG_DMEM_TCM_SIZE_MASK) 378 379 #define DCU_MEM_CONFIG_DMEM_CAC_SIZE_MASK (0xF00000U) 380 #define DCU_MEM_CONFIG_DMEM_CAC_SIZE_SHIFT (20U) 381 #define DCU_MEM_CONFIG_DMEM_CAC_SIZE_WIDTH (4U) 382 #define DCU_MEM_CONFIG_DMEM_CAC_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_DMEM_CAC_SIZE_SHIFT)) & DCU_MEM_CONFIG_DMEM_CAC_SIZE_MASK) 383 384 #define DCU_MEM_CONFIG_DMSS_BLK_MASK (0x3000000U) 385 #define DCU_MEM_CONFIG_DMSS_BLK_SHIFT (24U) 386 #define DCU_MEM_CONFIG_DMSS_BLK_WIDTH (2U) 387 #define DCU_MEM_CONFIG_DMSS_BLK(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_DMSS_BLK_SHIFT)) & DCU_MEM_CONFIG_DMSS_BLK_MASK) 388 389 #define DCU_MEM_CONFIG_DMEM_CAC_WAY_MASK (0x8000000U) 390 #define DCU_MEM_CONFIG_DMEM_CAC_WAY_SHIFT (27U) 391 #define DCU_MEM_CONFIG_DMEM_CAC_WAY_WIDTH (1U) 392 #define DCU_MEM_CONFIG_DMEM_CAC_WAY(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_DMEM_CAC_WAY_SHIFT)) & DCU_MEM_CONFIG_DMEM_CAC_WAY_MASK) 393 394 #define DCU_MEM_CONFIG_PECC_MASK (0x30000000U) 395 #define DCU_MEM_CONFIG_PECC_SHIFT (28U) 396 #define DCU_MEM_CONFIG_PECC_WIDTH (2U) 397 #define DCU_MEM_CONFIG_PECC(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_PECC_SHIFT)) & DCU_MEM_CONFIG_PECC_MASK) 398 399 #define DCU_MEM_CONFIG_DECC_MASK (0xC0000000U) 400 #define DCU_MEM_CONFIG_DECC_SHIFT (30U) 401 #define DCU_MEM_CONFIG_DECC_WIDTH (2U) 402 #define DCU_MEM_CONFIG_DECC(x) (((uint32_t)(((uint32_t)(x)) << DCU_MEM_CONFIG_DECC_SHIFT)) & DCU_MEM_CONFIG_DECC_MASK) 403 /*! @} */ 404 405 /*! @name MSS_CONFIG - MSS CONFIG Register */ 406 /*! @{ */ 407 408 #define DCU_MSS_CONFIG_NUM_QMAN_MASK (0x1FU) 409 #define DCU_MSS_CONFIG_NUM_QMAN_SHIFT (0U) 410 #define DCU_MSS_CONFIG_NUM_QMAN_WIDTH (5U) 411 #define DCU_MSS_CONFIG_NUM_QMAN(x) (((uint32_t)(((uint32_t)(x)) << DCU_MSS_CONFIG_NUM_QMAN_SHIFT)) & DCU_MSS_CONFIG_NUM_QMAN_MASK) 412 413 #define DCU_MSS_CONFIG_NUM_ICU_GRP_MASK (0xF0000U) 414 #define DCU_MSS_CONFIG_NUM_ICU_GRP_SHIFT (16U) 415 #define DCU_MSS_CONFIG_NUM_ICU_GRP_WIDTH (4U) 416 #define DCU_MSS_CONFIG_NUM_ICU_GRP(x) (((uint32_t)(((uint32_t)(x)) << DCU_MSS_CONFIG_NUM_ICU_GRP_SHIFT)) & DCU_MSS_CONFIG_NUM_ICU_GRP_MASK) 417 418 #define DCU_MSS_CONFIG_NUM_TIMER_MASK (0x300000U) 419 #define DCU_MSS_CONFIG_NUM_TIMER_SHIFT (20U) 420 #define DCU_MSS_CONFIG_NUM_TIMER_WIDTH (2U) 421 #define DCU_MSS_CONFIG_NUM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCU_MSS_CONFIG_NUM_TIMER_SHIFT)) & DCU_MSS_CONFIG_NUM_TIMER_MASK) 422 /*! @} */ 423 424 /*! @name OCM_STATUS - OCM STATUS Register */ 425 /*! @{ */ 426 427 #define DCU_OCM_STATUS_DBG_MODE_MASK (0x1U) 428 #define DCU_OCM_STATUS_DBG_MODE_SHIFT (0U) 429 #define DCU_OCM_STATUS_DBG_MODE_WIDTH (1U) 430 #define DCU_OCM_STATUS_DBG_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_DBG_MODE_SHIFT)) & DCU_OCM_STATUS_DBG_MODE_MASK) 431 432 #define DCU_OCM_STATUS_RST_DUR_DEBUG_MASK (0x2U) 433 #define DCU_OCM_STATUS_RST_DUR_DEBUG_SHIFT (1U) 434 #define DCU_OCM_STATUS_RST_DUR_DEBUG_WIDTH (1U) 435 #define DCU_OCM_STATUS_RST_DUR_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_RST_DUR_DEBUG_SHIFT)) & DCU_OCM_STATUS_RST_DUR_DEBUG_MASK) 436 437 #define DCU_OCM_STATUS_PMEM_WR_MASK (0x4U) 438 #define DCU_OCM_STATUS_PMEM_WR_SHIFT (2U) 439 #define DCU_OCM_STATUS_PMEM_WR_WIDTH (1U) 440 #define DCU_OCM_STATUS_PMEM_WR(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_PMEM_WR_SHIFT)) & DCU_OCM_STATUS_PMEM_WR_MASK) 441 442 #define DCU_OCM_STATUS_PCACHE_WR_MASK (0x8U) 443 #define DCU_OCM_STATUS_PCACHE_WR_SHIFT (3U) 444 #define DCU_OCM_STATUS_PCACHE_WR_WIDTH (1U) 445 #define DCU_OCM_STATUS_PCACHE_WR(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_PCACHE_WR_SHIFT)) & DCU_OCM_STATUS_PCACHE_WR_MASK) 446 447 #define DCU_OCM_STATUS_CORE_NOT_IDLE_MASK (0x20U) 448 #define DCU_OCM_STATUS_CORE_NOT_IDLE_SHIFT (5U) 449 #define DCU_OCM_STATUS_CORE_NOT_IDLE_WIDTH (1U) 450 #define DCU_OCM_STATUS_CORE_NOT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_CORE_NOT_IDLE_SHIFT)) & DCU_OCM_STATUS_CORE_NOT_IDLE_MASK) 451 452 #define DCU_OCM_STATUS_PACTIVE_TRANS_MASK (0x80U) 453 #define DCU_OCM_STATUS_PACTIVE_TRANS_SHIFT (7U) 454 #define DCU_OCM_STATUS_PACTIVE_TRANS_WIDTH (1U) 455 #define DCU_OCM_STATUS_PACTIVE_TRANS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_PACTIVE_TRANS_SHIFT)) & DCU_OCM_STATUS_PACTIVE_TRANS_MASK) 456 457 #define DCU_OCM_STATUS_TRAPE_INST_MASK (0x100U) 458 #define DCU_OCM_STATUS_TRAPE_INST_SHIFT (8U) 459 #define DCU_OCM_STATUS_TRAPE_INST_WIDTH (1U) 460 #define DCU_OCM_STATUS_TRAPE_INST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_TRAPE_INST_SHIFT)) & DCU_OCM_STATUS_TRAPE_INST_MASK) 461 462 #define DCU_OCM_STATUS_PMSS_IDLE_MASK (0x200U) 463 #define DCU_OCM_STATUS_PMSS_IDLE_SHIFT (9U) 464 #define DCU_OCM_STATUS_PMSS_IDLE_WIDTH (1U) 465 #define DCU_OCM_STATUS_PMSS_IDLE(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_PMSS_IDLE_SHIFT)) & DCU_OCM_STATUS_PMSS_IDLE_MASK) 466 467 #define DCU_OCM_STATUS_DACTIVE_TRANS_MASK (0x1000U) 468 #define DCU_OCM_STATUS_DACTIVE_TRANS_SHIFT (12U) 469 #define DCU_OCM_STATUS_DACTIVE_TRANS_WIDTH (1U) 470 #define DCU_OCM_STATUS_DACTIVE_TRANS(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_DACTIVE_TRANS_SHIFT)) & DCU_OCM_STATUS_DACTIVE_TRANS_MASK) 471 472 #define DCU_OCM_STATUS_DMSS_IDLE_OCEM_MASK (0x2000U) 473 #define DCU_OCM_STATUS_DMSS_IDLE_OCEM_SHIFT (13U) 474 #define DCU_OCM_STATUS_DMSS_IDLE_OCEM_WIDTH (1U) 475 #define DCU_OCM_STATUS_DMSS_IDLE_OCEM(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_DMSS_IDLE_OCEM_SHIFT)) & DCU_OCM_STATUS_DMSS_IDLE_OCEM_MASK) 476 477 #define DCU_OCM_STATUS_DMSS_SLAVE_ACT_MASK (0x8000U) 478 #define DCU_OCM_STATUS_DMSS_SLAVE_ACT_SHIFT (15U) 479 #define DCU_OCM_STATUS_DMSS_SLAVE_ACT_WIDTH (1U) 480 #define DCU_OCM_STATUS_DMSS_SLAVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_DMSS_SLAVE_ACT_SHIFT)) & DCU_OCM_STATUS_DMSS_SLAVE_ACT_MASK) 481 482 #define DCU_OCM_STATUS_WAIT_MASK (0x40000U) 483 #define DCU_OCM_STATUS_WAIT_SHIFT (18U) 484 #define DCU_OCM_STATUS_WAIT_WIDTH (1U) 485 #define DCU_OCM_STATUS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_WAIT_SHIFT)) & DCU_OCM_STATUS_WAIT_MASK) 486 487 #define DCU_OCM_STATUS_AUTH_IF_MASK (0xF0000000U) 488 #define DCU_OCM_STATUS_AUTH_IF_SHIFT (28U) 489 #define DCU_OCM_STATUS_AUTH_IF_WIDTH (4U) 490 #define DCU_OCM_STATUS_AUTH_IF(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_STATUS_AUTH_IF_SHIFT)) & DCU_OCM_STATUS_AUTH_IF_MASK) 491 /*! @} */ 492 493 /*! @name OCM_SA_BP_ST - OCM SA BP ST Register */ 494 /*! @{ */ 495 496 #define DCU_OCM_SA_BP_ST_SA_EXT_ST_MASK (0x3U) 497 #define DCU_OCM_SA_BP_ST_SA_EXT_ST_SHIFT (0U) 498 #define DCU_OCM_SA_BP_ST_SA_EXT_ST_WIDTH (2U) 499 #define DCU_OCM_SA_BP_ST_SA_EXT_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_EXT_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_EXT_ST_MASK) 500 501 #define DCU_OCM_SA_BP_ST_DMA_DA_ST_MASK (0x8U) 502 #define DCU_OCM_SA_BP_ST_DMA_DA_ST_SHIFT (3U) 503 #define DCU_OCM_SA_BP_ST_DMA_DA_ST_WIDTH (1U) 504 #define DCU_OCM_SA_BP_ST_DMA_DA_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_DMA_DA_ST_SHIFT)) & DCU_OCM_SA_BP_ST_DMA_DA_ST_MASK) 505 506 #define DCU_OCM_SA_BP_ST_SA_PA_ST_MASK (0x30U) 507 #define DCU_OCM_SA_BP_ST_SA_PA_ST_SHIFT (4U) 508 #define DCU_OCM_SA_BP_ST_SA_PA_ST_WIDTH (2U) 509 #define DCU_OCM_SA_BP_ST_SA_PA_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_PA_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_PA_ST_MASK) 510 511 #define DCU_OCM_SA_BP_ST_SA_DA_RD_ST_MASK (0x100U) 512 #define DCU_OCM_SA_BP_ST_SA_DA_RD_ST_SHIFT (8U) 513 #define DCU_OCM_SA_BP_ST_SA_DA_RD_ST_WIDTH (1U) 514 #define DCU_OCM_SA_BP_ST_SA_DA_RD_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_DA_RD_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_DA_RD_ST_MASK) 515 516 #define DCU_OCM_SA_BP_ST_SA_DA_WR_ST_MASK (0x1000U) 517 #define DCU_OCM_SA_BP_ST_SA_DA_WR_ST_SHIFT (12U) 518 #define DCU_OCM_SA_BP_ST_SA_DA_WR_ST_WIDTH (1U) 519 #define DCU_OCM_SA_BP_ST_SA_DA_WR_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_DA_WR_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_DA_WR_ST_MASK) 520 521 #define DCU_OCM_SA_BP_ST_SA_DVM_ST_MASK (0x20000U) 522 #define DCU_OCM_SA_BP_ST_SA_DVM_ST_SHIFT (17U) 523 #define DCU_OCM_SA_BP_ST_SA_DVM_ST_WIDTH (1U) 524 #define DCU_OCM_SA_BP_ST_SA_DVM_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_DVM_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_DVM_ST_MASK) 525 526 #define DCU_OCM_SA_BP_ST_SA_COMB_RD_ST_MASK (0x40000U) 527 #define DCU_OCM_SA_BP_ST_SA_COMB_RD_ST_SHIFT (18U) 528 #define DCU_OCM_SA_BP_ST_SA_COMB_RD_ST_WIDTH (1U) 529 #define DCU_OCM_SA_BP_ST_SA_COMB_RD_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_COMB_RD_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_COMB_RD_ST_MASK) 530 531 #define DCU_OCM_SA_BP_ST_SA_COMB_WR_ST_MASK (0x80000U) 532 #define DCU_OCM_SA_BP_ST_SA_COMB_WR_ST_SHIFT (19U) 533 #define DCU_OCM_SA_BP_ST_SA_COMB_WR_ST_WIDTH (1U) 534 #define DCU_OCM_SA_BP_ST_SA_COMB_WR_ST(x) (((uint32_t)(((uint32_t)(x)) << DCU_OCM_SA_BP_ST_SA_COMB_WR_ST_SHIFT)) & DCU_OCM_SA_BP_ST_SA_COMB_WR_ST_MASK) 535 /*! @} */ 536 537 /*! @name M_CONFIG - M CONFIG Register */ 538 /*! @{ */ 539 540 #define DCU_M_CONFIG_M0_WIDTH_MASK (0x7U) 541 #define DCU_M_CONFIG_M0_WIDTH_SHIFT (0U) 542 #define DCU_M_CONFIG_M0_WIDTH_WIDTH (3U) 543 #define DCU_M_CONFIG_M0_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_M_CONFIG_M0_WIDTH_SHIFT)) & DCU_M_CONFIG_M0_WIDTH_MASK) 544 545 #define DCU_M_CONFIG_M1_WIDTH_MASK (0x70U) 546 #define DCU_M_CONFIG_M1_WIDTH_SHIFT (4U) 547 #define DCU_M_CONFIG_M1_WIDTH_WIDTH (3U) 548 #define DCU_M_CONFIG_M1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_M_CONFIG_M1_WIDTH_SHIFT)) & DCU_M_CONFIG_M1_WIDTH_MASK) 549 550 #define DCU_M_CONFIG_EDP_WIDTH_MASK (0x700U) 551 #define DCU_M_CONFIG_EDP_WIDTH_SHIFT (8U) 552 #define DCU_M_CONFIG_EDP_WIDTH_WIDTH (3U) 553 #define DCU_M_CONFIG_EDP_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_M_CONFIG_EDP_WIDTH_SHIFT)) & DCU_M_CONFIG_EDP_WIDTH_MASK) 554 555 #define DCU_M_CONFIG_EPP_WIDTH_MASK (0x7000U) 556 #define DCU_M_CONFIG_EPP_WIDTH_SHIFT (12U) 557 #define DCU_M_CONFIG_EPP_WIDTH_WIDTH (3U) 558 #define DCU_M_CONFIG_EPP_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_M_CONFIG_EPP_WIDTH_SHIFT)) & DCU_M_CONFIG_EPP_WIDTH_MASK) 559 /*! @} */ 560 561 /*! @name S_CONFIG - S_CONFIG Register */ 562 /*! @{ */ 563 564 #define DCU_S_CONFIG_S0_WIDTH_MASK (0x7U) 565 #define DCU_S_CONFIG_S0_WIDTH_SHIFT (0U) 566 #define DCU_S_CONFIG_S0_WIDTH_WIDTH (3U) 567 #define DCU_S_CONFIG_S0_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_S_CONFIG_S0_WIDTH_SHIFT)) & DCU_S_CONFIG_S0_WIDTH_MASK) 568 569 #define DCU_S_CONFIG_S1_WIDTH_MASK (0x70U) 570 #define DCU_S_CONFIG_S1_WIDTH_SHIFT (4U) 571 #define DCU_S_CONFIG_S1_WIDTH_WIDTH (3U) 572 #define DCU_S_CONFIG_S1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_S_CONFIG_S1_WIDTH_SHIFT)) & DCU_S_CONFIG_S1_WIDTH_MASK) 573 574 #define DCU_S_CONFIG_S2_WIDTH_MASK (0x700U) 575 #define DCU_S_CONFIG_S2_WIDTH_SHIFT (8U) 576 #define DCU_S_CONFIG_S2_WIDTH_WIDTH (3U) 577 #define DCU_S_CONFIG_S2_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_S_CONFIG_S2_WIDTH_SHIFT)) & DCU_S_CONFIG_S2_WIDTH_MASK) 578 579 #define DCU_S_CONFIG_EDAP_WIDTH_MASK (0x7000U) 580 #define DCU_S_CONFIG_EDAP_WIDTH_SHIFT (12U) 581 #define DCU_S_CONFIG_EDAP_WIDTH_WIDTH (3U) 582 #define DCU_S_CONFIG_EDAP_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DCU_S_CONFIG_EDAP_WIDTH_SHIFT)) & DCU_S_CONFIG_EDAP_WIDTH_MASK) 583 /*! @} */ 584 585 /*! @name DEBUG_CONFIG - DEBUG CONFIG Register */ 586 /*! @{ */ 587 588 #define DCU_DEBUG_CONFIG_DVBP_MASK (0x6U) 589 #define DCU_DEBUG_CONFIG_DVBP_SHIFT (1U) 590 #define DCU_DEBUG_CONFIG_DVBP_WIDTH (2U) 591 #define DCU_DEBUG_CONFIG_DVBP(x) (((uint32_t)(((uint32_t)(x)) << DCU_DEBUG_CONFIG_DVBP_SHIFT)) & DCU_DEBUG_CONFIG_DVBP_MASK) 592 593 #define DCU_DEBUG_CONFIG_PROFILER_MASK (0x300U) 594 #define DCU_DEBUG_CONFIG_PROFILER_SHIFT (8U) 595 #define DCU_DEBUG_CONFIG_PROFILER_WIDTH (2U) 596 #define DCU_DEBUG_CONFIG_PROFILER(x) (((uint32_t)(((uint32_t)(x)) << DCU_DEBUG_CONFIG_PROFILER_SHIFT)) & DCU_DEBUG_CONFIG_PROFILER_MASK) 597 598 #define DCU_DEBUG_CONFIG_RTT_MASK (0x3000U) 599 #define DCU_DEBUG_CONFIG_RTT_SHIFT (12U) 600 #define DCU_DEBUG_CONFIG_RTT_WIDTH (2U) 601 #define DCU_DEBUG_CONFIG_RTT(x) (((uint32_t)(((uint32_t)(x)) << DCU_DEBUG_CONFIG_RTT_SHIFT)) & DCU_DEBUG_CONFIG_RTT_MASK) 602 603 #define DCU_DEBUG_CONFIG_APB_MASK (0x10000U) 604 #define DCU_DEBUG_CONFIG_APB_SHIFT (16U) 605 #define DCU_DEBUG_CONFIG_APB_WIDTH (1U) 606 #define DCU_DEBUG_CONFIG_APB(x) (((uint32_t)(((uint32_t)(x)) << DCU_DEBUG_CONFIG_APB_SHIFT)) & DCU_DEBUG_CONFIG_APB_MASK) 607 /*! @} */ 608 609 /*! @name CORE_VERSION - CORE VERSION Register */ 610 /*! @{ */ 611 612 #define DCU_CORE_VERSION_DSP_RTL_REVISION_MASK (0xFU) 613 #define DCU_CORE_VERSION_DSP_RTL_REVISION_SHIFT (0U) 614 #define DCU_CORE_VERSION_DSP_RTL_REVISION_WIDTH (4U) 615 #define DCU_CORE_VERSION_DSP_RTL_REVISION(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_VERSION_DSP_RTL_REVISION_SHIFT)) & DCU_CORE_VERSION_DSP_RTL_REVISION_MASK) 616 617 #define DCU_CORE_VERSION_DSP_RTL_VERSION_MASK (0xFFF0U) 618 #define DCU_CORE_VERSION_DSP_RTL_VERSION_SHIFT (4U) 619 #define DCU_CORE_VERSION_DSP_RTL_VERSION_WIDTH (12U) 620 #define DCU_CORE_VERSION_DSP_RTL_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_VERSION_DSP_RTL_VERSION_SHIFT)) & DCU_CORE_VERSION_DSP_RTL_VERSION_MASK) 621 622 #define DCU_CORE_VERSION_DSP_CORE_TYPE_MASK (0xFFFF0000U) 623 #define DCU_CORE_VERSION_DSP_CORE_TYPE_SHIFT (16U) 624 #define DCU_CORE_VERSION_DSP_CORE_TYPE_WIDTH (16U) 625 #define DCU_CORE_VERSION_DSP_CORE_TYPE(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_VERSION_DSP_CORE_TYPE_SHIFT)) & DCU_CORE_VERSION_DSP_CORE_TYPE_MASK) 626 /*! @} */ 627 628 /*! @name CORE_ID - CORE ID Register */ 629 /*! @{ */ 630 631 #define DCU_CORE_ID_CORE_ID_MASK (0xFFFFFFFFU) 632 #define DCU_CORE_ID_CORE_ID_SHIFT (0U) 633 #define DCU_CORE_ID_CORE_ID_WIDTH (32U) 634 #define DCU_CORE_ID_CORE_ID(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_ID_CORE_ID_SHIFT)) & DCU_CORE_ID_CORE_ID_MASK) 635 /*! @} */ 636 637 /*! @name CORE_CONFIG - CORE CONFIG Register */ 638 /*! @{ */ 639 640 #define DCU_CORE_CONFIG_SPU_XTEND_MASK (0x1U) 641 #define DCU_CORE_CONFIG_SPU_XTEND_SHIFT (0U) 642 #define DCU_CORE_CONFIG_SPU_XTEND_WIDTH (1U) 643 #define DCU_CORE_CONFIG_SPU_XTEND(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_SPU_XTEND_SHIFT)) & DCU_CORE_CONFIG_SPU_XTEND_MASK) 644 645 #define DCU_CORE_CONFIG_VPU_XTEND_MASK (0x2U) 646 #define DCU_CORE_CONFIG_VPU_XTEND_SHIFT (1U) 647 #define DCU_CORE_CONFIG_VPU_XTEND_WIDTH (1U) 648 #define DCU_CORE_CONFIG_VPU_XTEND(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_VPU_XTEND_SHIFT)) & DCU_CORE_CONFIG_VPU_XTEND_MASK) 649 650 #define DCU_CORE_CONFIG_BTB_ENTRIES_MASK (0x30U) 651 #define DCU_CORE_CONFIG_BTB_ENTRIES_SHIFT (4U) 652 #define DCU_CORE_CONFIG_BTB_ENTRIES_WIDTH (2U) 653 #define DCU_CORE_CONFIG_BTB_ENTRIES(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_BTB_ENTRIES_SHIFT)) & DCU_CORE_CONFIG_BTB_ENTRIES_MASK) 654 655 #define DCU_CORE_CONFIG_BTB_WAYS_MASK (0x80U) 656 #define DCU_CORE_CONFIG_BTB_WAYS_SHIFT (7U) 657 #define DCU_CORE_CONFIG_BTB_WAYS_WIDTH (1U) 658 #define DCU_CORE_CONFIG_BTB_WAYS(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_BTB_WAYS_SHIFT)) & DCU_CORE_CONFIG_BTB_WAYS_MASK) 659 660 #define DCU_CORE_CONFIG_SFP_MASK (0x200U) 661 #define DCU_CORE_CONFIG_SFP_SHIFT (9U) 662 #define DCU_CORE_CONFIG_SFP_WIDTH (1U) 663 #define DCU_CORE_CONFIG_SFP(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_SFP_SHIFT)) & DCU_CORE_CONFIG_SFP_MASK) 664 665 #define DCU_CORE_CONFIG_HPF_MASK (0x400U) 666 #define DCU_CORE_CONFIG_HPF_SHIFT (10U) 667 #define DCU_CORE_CONFIG_HPF_WIDTH (1U) 668 #define DCU_CORE_CONFIG_HPF(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_HPF_SHIFT)) & DCU_CORE_CONFIG_HPF_MASK) 669 670 #define DCU_CORE_CONFIG_NUM_VCU_MASK (0x10000U) 671 #define DCU_CORE_CONFIG_NUM_VCU_SHIFT (16U) 672 #define DCU_CORE_CONFIG_NUM_VCU_WIDTH (1U) 673 #define DCU_CORE_CONFIG_NUM_VCU(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_NUM_VCU_SHIFT)) & DCU_CORE_CONFIG_NUM_VCU_MASK) 674 675 #define DCU_CORE_CONFIG_LVPU_MASK (0x20000U) 676 #define DCU_CORE_CONFIG_LVPU_SHIFT (17U) 677 #define DCU_CORE_CONFIG_LVPU_WIDTH (1U) 678 #define DCU_CORE_CONFIG_LVPU(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_LVPU_SHIFT)) & DCU_CORE_CONFIG_LVPU_MASK) 679 680 #define DCU_CORE_CONFIG_VEC_MPY_MASK (0x100000U) 681 #define DCU_CORE_CONFIG_VEC_MPY_SHIFT (20U) 682 #define DCU_CORE_CONFIG_VEC_MPY_WIDTH (1U) 683 #define DCU_CORE_CONFIG_VEC_MPY(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_VEC_MPY_SHIFT)) & DCU_CORE_CONFIG_VEC_MPY_MASK) 684 685 #define DCU_CORE_CONFIG_VEC_MPY_XTD_MASK (0x200000U) 686 #define DCU_CORE_CONFIG_VEC_MPY_XTD_SHIFT (21U) 687 #define DCU_CORE_CONFIG_VEC_MPY_XTD_WIDTH (1U) 688 #define DCU_CORE_CONFIG_VEC_MPY_XTD(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_VEC_MPY_XTD_SHIFT)) & DCU_CORE_CONFIG_VEC_MPY_XTD_MASK) 689 690 #define DCU_CORE_CONFIG_VSP_FP_MASK (0xC00000U) 691 #define DCU_CORE_CONFIG_VSP_FP_SHIFT (22U) 692 #define DCU_CORE_CONFIG_VSP_FP_WIDTH (2U) 693 #define DCU_CORE_CONFIG_VSP_FP(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_VSP_FP_SHIFT)) & DCU_CORE_CONFIG_VSP_FP_MASK) 694 695 #define DCU_CORE_CONFIG_VHP_FP_MASK (0x1000000U) 696 #define DCU_CORE_CONFIG_VHP_FP_SHIFT (24U) 697 #define DCU_CORE_CONFIG_VHP_FP_WIDTH (1U) 698 #define DCU_CORE_CONFIG_VHP_FP(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_VHP_FP_SHIFT)) & DCU_CORE_CONFIG_VHP_FP_MASK) 699 700 #define DCU_CORE_CONFIG_NL_MASK (0x2000000U) 701 #define DCU_CORE_CONFIG_NL_SHIFT (25U) 702 #define DCU_CORE_CONFIG_NL_WIDTH (1U) 703 #define DCU_CORE_CONFIG_NL(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_NL_SHIFT)) & DCU_CORE_CONFIG_NL_MASK) 704 705 #define DCU_CORE_CONFIG_BNN_MASK (0x4000000U) 706 #define DCU_CORE_CONFIG_BNN_SHIFT (26U) 707 #define DCU_CORE_CONFIG_BNN_WIDTH (1U) 708 #define DCU_CORE_CONFIG_BNN(x) (((uint32_t)(((uint32_t)(x)) << DCU_CORE_CONFIG_BNN_SHIFT)) & DCU_CORE_CONFIG_BNN_MASK) 709 /*! @} */ 710 711 /*! 712 * @} 713 */ /* end of group DCU_Register_Masks */ 714 715 /*! 716 * @} 717 */ /* end of group DCU_Peripheral_Access_Layer */ 718 719 #endif /* #if !defined(S32Z2_DCU_H_) */ 720
