Searched refs:DCDC_RMW_REG0 (Results 1 – 1 of 1) sorted by relevance
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/ |
| D | MKW40Z4_extension.h | 3705 #define DCDC_RMW_REG0(base, mask, value) (DCDC_WR_REG0(base, (DCDC_RD_REG0(base) & ~(mask)) | (valu… macro
3726 #define DCDC_WR_REG0_DCDC_DISABLE_AUTO_CLK_SWITCH(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_…
3741 #define DCDC_WR_REG0_DCDC_SEL_CLK(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_SEL_CLK_MASK, DC…
3757 #define DCDC_WR_REG0_DCDC_PWD_OSC_INT(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_PWD_OSC_INT_…
3773 #define DCDC_WR_REG0_DCDC_LP_DF_CMP_ENABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_DF_C…
3789 #define DCDC_WR_REG0_DCDC_VBAT_DIV_CTRL(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_VBAT_DIV_C…
3811 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_L(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_…
3833 #define DCDC_WR_REG0_DCDC_LP_STATE_HYS_H(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_DCDC_LP_STATE_…
3848 #define DCDC_WR_REG0_HYST_LP_COMP_ADJ(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_COMP_ADJ_…
3863 #define DCDC_WR_REG0_HYST_LP_CMP_DISABLE(base, value) (DCDC_RMW_REG0(base, DCDC_REG0_HYST_LP_CMP_DI…
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