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Searched refs:DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (Results 1 – 25 of 31) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.h524 … base->REG3 |= DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK | DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnterLowPowerMode()
568 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0StandbyModeTargetVoltage()
631 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
696 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
700 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_dcdc.h335 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
410 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
584 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
588 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_dcdc.h335 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
410 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
584 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
588 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_dcdc.h335 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
410 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
584 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
588 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_dcdc.h335 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0LowPowerModeTargetVoltage()
410 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_SetVDD1P0BuckModeTargetVoltage()
584 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
588 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_EnableVDD1P0TargetVoltageStepping()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c583 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_AdjustTargetVoltage()
633 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_AdjustRunTargetVoltage()
683 base->REG3 &= ~DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_AdjustLowPowerTargetVoltage()
Dfsl_dcdc.h527 base->REG3 |= DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK; in DCDC_LockVdd1p0TargetVoltage()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h26169 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
26175 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
DMIMXRT1175_cm7.h26172 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
26178 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25860 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
25866 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
DMIMXRT1165_cm4.h25857 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
25863 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26172 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
26178 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h27862 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
27868 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
DMIMXRT1166_cm7.h27865 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
27871 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h28171 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
28177 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
DMIMXRT1173_cm7.h28174 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
28180 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h28177 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
28183 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h28179 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
28185 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
DMIMXRT1176_cm4.h28176 #define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U) macro
28182 …int32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)

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