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Searched refs:DCDC_REG24_OK_COUNT_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h26357 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
26359 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
DMIMXRT1175_cm7.h26360 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
26362 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h26048 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
26050 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
DMIMXRT1165_cm4.h26045 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
26047 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26360 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
26362 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h28050 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28052 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
DMIMXRT1166_cm7.h28053 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28055 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h28359 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28361 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
DMIMXRT1173_cm7.h28362 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28364 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h28365 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28367 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h28367 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28369 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
DMIMXRT1176_cm4.h28364 #define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU) macro
28366 … (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)