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Searched refs:DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (Results 1 – 19 of 19) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.c501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK; in DCDC_BootIntoDCM()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h25987 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
25993 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
DMIMXRT1175_cm7.h25990 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
25996 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25678 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
25684 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
DMIMXRT1165_cm4.h25675 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
25681 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h25990 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
25996 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h27680 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
27686 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
DMIMXRT1166_cm7.h27683 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
27689 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h27989 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
27995 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
DMIMXRT1173_cm7.h27992 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
27998 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h27995 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
28001 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h27997 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
28003 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
DMIMXRT1176_cm4.h27994 #define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U) macro
28000 …int32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)