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Searched refs:DCDC_REG19_ANA_STBY_TRG_SP3_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h26005 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
26007 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
DMIMXRT1165_cm7.h26008 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
26010 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h26320 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
26322 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h26317 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
26319 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
DMIMXRT1175_cm7.h26320 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
26322 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h28322 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28324 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
DMIMXRT1173_cm4.h28319 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28321 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm7.h28013 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28015 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
DMIMXRT1166_cm4.h28010 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28012 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h28325 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28327 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h28327 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28329 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
DMIMXRT1176_cm4.h28324 #define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU) macro
28326 …int32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)