Searched refs:DCDC_REG18_ANA_STBY_TRG_SP2_MASK (Results 1 – 12 of 12) sorted by relevance
26309 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro26311 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
26312 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro26314 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
26000 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro26002 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
25997 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro25999 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28002 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28004 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28005 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28007 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28311 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28313 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28314 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28316 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28317 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28319 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28319 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28321 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
28316 #define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU) macro28318 …int32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
