Searched refs:DCDC_REG17_ANA_STBY_TRG_SP1_MASK (Results 1 – 12 of 12) sorted by relevance
26301 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro26303 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
26304 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro26306 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
25992 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro25994 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
25989 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro25991 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
27994 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro27996 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
27997 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro27999 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28303 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro28305 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28306 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro28308 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28309 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro28311 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28311 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro28313 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
28308 #define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU) macro28310 …int32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
