Home
last modified time | relevance | path

Searched refs:DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (Results 1 – 25 of 41) sorted by relevance

12

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_dcdc.c197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
202 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
206 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_dcdc.c197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
202 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
206 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_dcdc.c197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
202 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
206 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_dcdc.c197 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
202 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
206 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.c250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
259 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c205 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | in DCDC_SetClockSource()
210 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK; in DCDC_SetClockSource()
214 …tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_M… in DCDC_SetClockSource()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h7920 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
7926 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h8634 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
8640 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h10174 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
10180 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h10194 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
10200 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h11216 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
11222 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h12287 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
12293 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h12001 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
12007 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h12289 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
12295 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h12655 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
12661 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h13519 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
13525 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h13441 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
13447 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h25865 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
25872 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25556 #define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U) macro
25563 …int32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)

12