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Searched refs:DCDC_CTRL0_ENABLE_MASK (Results 1 – 20 of 20) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.c110 tmp32 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c110 base->CTRL0 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h25746 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
25752 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
DMIMXRT1175_cm7.h25749 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
25755 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25437 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
25443 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
DMIMXRT1165_cm4.h25434 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
25440 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h25749 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
25755 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h27439 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27445 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
DMIMXRT1166_cm7.h27442 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27448 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h27748 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27754 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
DMIMXRT1173_cm7.h27751 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27757 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h27754 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27760 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h27756 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27762 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
DMIMXRT1176_cm4.h27753 #define DCDC_CTRL0_ENABLE_MASK (0x1U) macro
27759 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)