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Searched refs:DCDC_CTRL0_CONTROL_MODE_MASK (Results 1 – 17 of 17) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1175/
Dfsl_pm_device.c984 if ((DCDC->CTRL0 & DCDC_CTRL0_CONTROL_MODE_MASK) == 0UL) in PM_DEV_SetPowerSupplyControlBySetpoint()
987 DCDC->CTRL0 |= DCDC_CTRL0_CONTROL_MODE_MASK; in PM_DEV_SetPowerSupplyControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1171/
Dfsl_pm_device.c984 if ((DCDC->CTRL0 & DCDC_CTRL0_CONTROL_MODE_MASK) == 0UL) in PM_DEV_SetPowerSupplyControlBySetpoint()
987 DCDC->CTRL0 |= DCDC_CTRL0_CONTROL_MODE_MASK; in PM_DEV_SetPowerSupplyControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1172/
Dfsl_pm_device.c984 if ((DCDC->CTRL0 & DCDC_CTRL0_CONTROL_MODE_MASK) == 0UL) in PM_DEV_SetPowerSupplyControlBySetpoint()
987 DCDC->CTRL0 |= DCDC_CTRL0_CONTROL_MODE_MASK; in PM_DEV_SetPowerSupplyControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1176/
Dfsl_pm_device.c984 if ((DCDC->CTRL0 & DCDC_CTRL0_CONTROL_MODE_MASK) == 0UL) in PM_DEV_SetPowerSupplyControlBySetpoint()
987 DCDC->CTRL0 |= DCDC_CTRL0_CONTROL_MODE_MASK; in PM_DEV_SetPowerSupplyControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/components/power_manager/devices/MIMXRT1173/
Dfsl_pm_device.c984 if ((DCDC->CTRL0 & DCDC_CTRL0_CONTROL_MODE_MASK) == 0UL) in PM_DEV_SetPowerSupplyControlBySetpoint()
987 DCDC->CTRL0 |= DCDC_CTRL0_CONTROL_MODE_MASK; in PM_DEV_SetPowerSupplyControlBySetpoint()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/
DMIMXRT1175_cm4.h25805 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
25811 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
DMIMXRT1175_cm7.h25808 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
25814 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm7.h25496 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
25502 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
DMIMXRT1165_cm4.h25493 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
25499 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/
DMIMXRT1171.h25808 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
25814 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/
DMIMXRT1166_cm4.h27498 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27504 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
DMIMXRT1166_cm7.h27501 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27507 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm4.h27807 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27813 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
DMIMXRT1173_cm7.h27810 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27816 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/
DMIMXRT1172.h27813 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27819 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/
DMIMXRT1176_cm7.h27815 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27821 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
DMIMXRT1176_cm4.h27812 #define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U) macro
27818 … (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)