Searched refs:DCDCC3 (Results 1 – 4 of 4) sorted by relevance
746 …base->DCDCC3 |= (SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK | SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABLE… in SPM_EnableVddxStepLock()750 …base->DCDCC3 &= ~(SPM_DCDCC3_DCDC_VDD1P8CTRL_DISABLE_STEP_MASK | SPM_DCDCC3_DCDC_VDD1P2CTRL_DISABL… in SPM_EnableVddxStepLock()769 base->DCDCC3 = (base->DCDCC3 & ~0xE000000U) | ((uint32_t)(strength) << 25); in SPM_SetDcdcDriveStrength()786 base->DCDCC3 |= SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK; in SPM_SplitDcdcClockFreq()790 base->DCDCC3 &= ~SPM_DCDCC3_DCDC_MINPWR_DC_HALFCLK_MASK; in SPM_SplitDcdcClockFreq()840 base->DCDCC3 |= SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; in SPC_BypassDcdcAdcMeasure()844 base->DCDCC3 &= ~SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; in SPC_BypassDcdcAdcMeasure()
217 …base->DCDCC3 = (base->DCDCC3 & ~SPM_DCDCC3_DCDC_VBAT_VALUE_MASK) | SPM_DCDCC3_DCDC_VBAT_VALUE(valu… in SPM_BypassDcdcBattMonitor()219 base->DCDCC3 |= SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; in SPM_BypassDcdcBattMonitor()223 base->DCDCC3 &= ~SPM_DCDCC3_DCDC_BYPASS_ADC_MEAS_MASK; in SPM_BypassDcdcBattMonitor()
19685 __IO uint32_t DCDCC3; /**< DCDC Control Register 3, offset: 0x314 */ member
19795 __IO uint32_t DCDCC3; /**< DCDC Control Register 3, offset: 0x314 */ member
