1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_DBG.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_DBG 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_DBG_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_DBG_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- DBG Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup DBG_Peripheral_Access_Layer DBG Peripheral Access Layer 68 * @{ 69 */ 70 71 /** DBG - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t DBG_DDAM; /**< DDMA Breakpoint Register, offset: 0x0 */ 74 __O uint32_t DBGACS; /**< Error Access Control Register, offset: 0x4 */ 75 __IO uint32_t DBG_DDC; /**< DDMA Breakpoint Control Register, offset: 0x8 */ 76 __IO uint32_t DBG_DDS; /**< DDMA Breakpoint Status Register, offset: 0xC */ 77 __IO uint32_t CENSIRQ; /**< Critical Error Interrupt Requests Register, offset: 0x10 */ 78 __IO uint32_t CENSIRQ2; /**< Critical Errors Interrupt 2 Register, offset: 0x14 */ 79 __IO uint32_t CWDOGIRQ; /**< Critical Error Interrupt Requests Register, offset: 0x18 */ 80 __IO uint32_t NENSIRQ; /**< Normal Error Interrupt Requests Register, offset: 0x1C */ 81 __IO uint32_t TIMER_IRQ; /**< Timer Interrupt Source Register, offset: 0x20 */ 82 __IO uint32_t DMA_IRQ; /**< DMA Interrupt Source Register, offset: 0x24 */ 83 __IO uint32_t POSCINT; /**< Posted Core Interrupt Register, offset: 0x28 */ 84 uint8_t RESERVED_0[4]; 85 __I uint32_t NQBIRQ; /**< Normal QMAN and Buffers Interrupt Register, offset: 0x30 */ 86 uint8_t RESERVED_1[8]; 87 __IO uint32_t NENSIRQ_M; /**< Normal Error Interrupt Request Mask Register, offset: 0x3C */ 88 __IO uint32_t TIMER_IRQ_M; /**< Timer Interrupt Mask Register, offset: 0x40 */ 89 __IO uint32_t NQBIRQ_M; /**< Normal QMAN and Buffers Interrupt Mask Register, offset: 0x44 */ 90 uint8_t RESERVED_2[8]; 91 __IO uint32_t DBG_STACK_START; /**< Stack Violation Start Address Register, offset: 0x50 */ 92 __IO uint32_t DBG_STACK_END; /**< Stack Violation End Address Register, offset: 0x54 */ 93 __IO uint32_t DBG_DUNMPD_MSK; /**< DBG DMSS Unmapped Access Mask Register, offset: 0x58 */ 94 __IO uint32_t DBG_DUNMPD; /**< DMSS Unmapped Access Status Register, offset: 0x5C */ 95 __O uint32_t CENSIRQ_S; /**< Critical Error Interrupt Request Shadow Register, offset: 0x60 */ 96 __O uint32_t CENSIRQ2_S; /**< Critical Error Interrupt Request 2 Shadow Register, offset: 0x64 */ 97 __O uint32_t CWDOGIRQ_S; /**< Critical Error Interrupt Request Shadow Register, offset: 0x68 */ 98 __O uint32_t NENSIRQ_S; /**< Normal Error Interrupt Requests Shadow Register, offset: 0x6C */ 99 __O uint32_t TIMER_IRQ_S; /**< Timer Interrupt Shadow Register, offset: 0x70 */ 100 __O uint32_t DMA_IRQ_S; /**< DMA Interrupt Shadow Register, offset: 0x74 */ 101 uint8_t RESERVED_3[56]; 102 __IO uint32_t DBG_DESC_ID; /**< DBG DESC ID Register, offset: 0xB0 */ 103 __IO uint32_t DBG_QMAN_ID; /**< DBG QMAN ID Register, offset: 0xB4 */ 104 uint8_t RESERVED_4[8]; 105 __IO uint32_t XCI_COR; /**< MSS Acknowledge Control Register, offset: 0xC0 */ 106 } DBG_Type, *DBG_MemMapPtr; 107 108 /** Number of instances of the DBG module. */ 109 #define DBG_INSTANCE_COUNT (1u) 110 111 /* DBG - Peripheral instance base addresses */ 112 /** Peripheral CEVA_SPF2__DBG base address */ 113 #define IP_CEVA_SPF2__DBG_BASE (0x24400D00u) 114 /** Peripheral CEVA_SPF2__DBG base pointer */ 115 #define IP_CEVA_SPF2__DBG ((DBG_Type *)IP_CEVA_SPF2__DBG_BASE) 116 /** Array initializer of DBG peripheral base addresses */ 117 #define IP_DBG_BASE_ADDRS { IP_CEVA_SPF2__DBG_BASE } 118 /** Array initializer of DBG peripheral base pointers */ 119 #define IP_DBG_BASE_PTRS { IP_CEVA_SPF2__DBG } 120 121 /* ---------------------------------------------------------------------------- 122 -- DBG Register Masks 123 ---------------------------------------------------------------------------- */ 124 125 /*! 126 * @addtogroup DBG_Register_Masks DBG Register Masks 127 * @{ 128 */ 129 130 /*! @name DBG_DDAM - DDMA Breakpoint Register */ 131 /*! @{ */ 132 133 #define DBG_DBG_DDAM_DMADAM_MASK (0xFFFFFFFFU) 134 #define DBG_DBG_DDAM_DMADAM_SHIFT (0U) 135 #define DBG_DBG_DDAM_DMADAM_WIDTH (32U) 136 #define DBG_DBG_DDAM_DMADAM(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DDAM_DMADAM_SHIFT)) & DBG_DBG_DDAM_DMADAM_MASK) 137 /*! @} */ 138 139 /*! @name DBGACS - Error Access Control Register */ 140 /*! @{ */ 141 142 #define DBG_DBGACS_DBG_ACS_MASK (0xFFFFU) 143 #define DBG_DBGACS_DBG_ACS_SHIFT (0U) 144 #define DBG_DBGACS_DBG_ACS_WIDTH (16U) 145 #define DBG_DBGACS_DBG_ACS(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBGACS_DBG_ACS_SHIFT)) & DBG_DBGACS_DBG_ACS_MASK) 146 /*! @} */ 147 148 /*! @name DBG_DDC - DDMA Breakpoint Control Register */ 149 /*! @{ */ 150 151 #define DBG_DBG_DDC_DMADAMS_MASK (0x7U) 152 #define DBG_DBG_DDC_DMADAMS_SHIFT (0U) 153 #define DBG_DBG_DDC_DMADAMS_WIDTH (3U) 154 #define DBG_DBG_DDC_DMADAMS(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DDC_DMADAMS_SHIFT)) & DBG_DBG_DDC_DMADAMS_MASK) 155 /*! @} */ 156 157 /*! @name DBG_DDS - DDMA Breakpoint Status Register */ 158 /*! @{ */ 159 160 #define DBG_DBG_DDS_DMADAMST_MASK (0x7U) 161 #define DBG_DBG_DDS_DMADAMST_SHIFT (0U) 162 #define DBG_DBG_DDS_DMADAMST_WIDTH (3U) 163 #define DBG_DBG_DDS_DMADAMST(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DDS_DMADAMST_SHIFT)) & DBG_DBG_DDS_DMADAMST_MASK) 164 /*! @} */ 165 166 /*! @name CENSIRQ - Critical Error Interrupt Requests Register */ 167 /*! @{ */ 168 169 #define DBG_CENSIRQ_CNSE_MASK (0x1U) 170 #define DBG_CENSIRQ_CNSE_SHIFT (0U) 171 #define DBG_CENSIRQ_CNSE_WIDTH (1U) 172 #define DBG_CENSIRQ_CNSE(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_CNSE_SHIFT)) & DBG_CENSIRQ_CNSE_MASK) 173 174 #define DBG_CENSIRQ_CNSIPV_MASK (0x2U) 175 #define DBG_CENSIRQ_CNSIPV_SHIFT (1U) 176 #define DBG_CENSIRQ_CNSIPV_WIDTH (1U) 177 #define DBG_CENSIRQ_CNSIPV(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_CNSIPV_SHIFT)) & DBG_CENSIRQ_CNSIPV_MASK) 178 179 #define DBG_CENSIRQ_CNSILOP_MASK (0x4U) 180 #define DBG_CENSIRQ_CNSILOP_SHIFT (2U) 181 #define DBG_CENSIRQ_CNSILOP_WIDTH (1U) 182 #define DBG_CENSIRQ_CNSILOP(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_CNSILOP_SHIFT)) & DBG_CENSIRQ_CNSILOP_MASK) 183 184 #define DBG_CENSIRQ_CNSIRE_MASK (0x10U) 185 #define DBG_CENSIRQ_CNSIRE_SHIFT (4U) 186 #define DBG_CENSIRQ_CNSIRE_WIDTH (1U) 187 #define DBG_CENSIRQ_CNSIRE(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_CNSIRE_SHIFT)) & DBG_CENSIRQ_CNSIRE_MASK) 188 189 #define DBG_CENSIRQ_IN_PRIV_MASK (0x100U) 190 #define DBG_CENSIRQ_IN_PRIV_SHIFT (8U) 191 #define DBG_CENSIRQ_IN_PRIV_WIDTH (1U) 192 #define DBG_CENSIRQ_IN_PRIV(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_IN_PRIV_SHIFT)) & DBG_CENSIRQ_IN_PRIV_MASK) 193 194 #define DBG_CENSIRQ_OUT_PRIV_MASK (0x200U) 195 #define DBG_CENSIRQ_OUT_PRIV_SHIFT (9U) 196 #define DBG_CENSIRQ_OUT_PRIV_WIDTH (1U) 197 #define DBG_CENSIRQ_OUT_PRIV(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_OUT_PRIV_SHIFT)) & DBG_CENSIRQ_OUT_PRIV_MASK) 198 199 #define DBG_CENSIRQ_LD_PRIV_ACC_MASK (0x400U) 200 #define DBG_CENSIRQ_LD_PRIV_ACC_SHIFT (10U) 201 #define DBG_CENSIRQ_LD_PRIV_ACC_WIDTH (1U) 202 #define DBG_CENSIRQ_LD_PRIV_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_LD_PRIV_ACC_SHIFT)) & DBG_CENSIRQ_LD_PRIV_ACC_MASK) 203 204 #define DBG_CENSIRQ_ST_PRIV_ACC_MASK (0x800U) 205 #define DBG_CENSIRQ_ST_PRIV_ACC_SHIFT (11U) 206 #define DBG_CENSIRQ_ST_PRIV_ACC_WIDTH (1U) 207 #define DBG_CENSIRQ_ST_PRIV_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_ST_PRIV_ACC_SHIFT)) & DBG_CENSIRQ_ST_PRIV_ACC_MASK) 208 209 #define DBG_CENSIRQ_LD_BLANK_ACC_MASK (0x1000U) 210 #define DBG_CENSIRQ_LD_BLANK_ACC_SHIFT (12U) 211 #define DBG_CENSIRQ_LD_BLANK_ACC_WIDTH (1U) 212 #define DBG_CENSIRQ_LD_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_LD_BLANK_ACC_SHIFT)) & DBG_CENSIRQ_LD_BLANK_ACC_MASK) 213 214 #define DBG_CENSIRQ_ST_BLANK_ACC_MASK (0x2000U) 215 #define DBG_CENSIRQ_ST_BLANK_ACC_SHIFT (13U) 216 #define DBG_CENSIRQ_ST_BLANK_ACC_WIDTH (1U) 217 #define DBG_CENSIRQ_ST_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_ST_BLANK_ACC_SHIFT)) & DBG_CENSIRQ_ST_BLANK_ACC_MASK) 218 219 #define DBG_CENSIRQ_LD_RG_CROS_MASK (0x4000U) 220 #define DBG_CENSIRQ_LD_RG_CROS_SHIFT (14U) 221 #define DBG_CENSIRQ_LD_RG_CROS_WIDTH (1U) 222 #define DBG_CENSIRQ_LD_RG_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_LD_RG_CROS_SHIFT)) & DBG_CENSIRQ_LD_RG_CROS_MASK) 223 224 #define DBG_CENSIRQ_ST_RG_CROS_MASK (0x8000U) 225 #define DBG_CENSIRQ_ST_RG_CROS_SHIFT (15U) 226 #define DBG_CENSIRQ_ST_RG_CROS_WIDTH (1U) 227 #define DBG_CENSIRQ_ST_RG_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_ST_RG_CROS_SHIFT)) & DBG_CENSIRQ_ST_RG_CROS_MASK) 228 229 #define DBG_CENSIRQ_UNMAPPED_EXCPTN_MASK (0x10000U) 230 #define DBG_CENSIRQ_UNMAPPED_EXCPTN_SHIFT (16U) 231 #define DBG_CENSIRQ_UNMAPPED_EXCPTN_WIDTH (1U) 232 #define DBG_CENSIRQ_UNMAPPED_EXCPTN(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_UNMAPPED_EXCPTN_SHIFT)) & DBG_CENSIRQ_UNMAPPED_EXCPTN_MASK) 233 234 #define DBG_CENSIRQ_STACK_VIOL_EXCPTN_MASK (0x20000U) 235 #define DBG_CENSIRQ_STACK_VIOL_EXCPTN_SHIFT (17U) 236 #define DBG_CENSIRQ_STACK_VIOL_EXCPTN_WIDTH (1U) 237 #define DBG_CENSIRQ_STACK_VIOL_EXCPTN(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_STACK_VIOL_EXCPTN_SHIFT)) & DBG_CENSIRQ_STACK_VIOL_EXCPTN_MASK) 238 239 #define DBG_CENSIRQ_EXC_E_MASK (0x40000U) 240 #define DBG_CENSIRQ_EXC_E_SHIFT (18U) 241 #define DBG_CENSIRQ_EXC_E_WIDTH (1U) 242 #define DBG_CENSIRQ_EXC_E(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_EXC_E_SHIFT)) & DBG_CENSIRQ_EXC_E_MASK) 243 244 #define DBG_CENSIRQ_ER_EXOK_MASK (0x80000U) 245 #define DBG_CENSIRQ_ER_EXOK_SHIFT (19U) 246 #define DBG_CENSIRQ_ER_EXOK_WIDTH (1U) 247 #define DBG_CENSIRQ_ER_EXOK(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_ER_EXOK_SHIFT)) & DBG_CENSIRQ_ER_EXOK_MASK) 248 249 #define DBG_CENSIRQ_LD_IDM_CROS_MASK (0x100000U) 250 #define DBG_CENSIRQ_LD_IDM_CROS_SHIFT (20U) 251 #define DBG_CENSIRQ_LD_IDM_CROS_WIDTH (1U) 252 #define DBG_CENSIRQ_LD_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_LD_IDM_CROS_SHIFT)) & DBG_CENSIRQ_LD_IDM_CROS_MASK) 253 254 #define DBG_CENSIRQ_ST_IDM_CROS_MASK (0x200000U) 255 #define DBG_CENSIRQ_ST_IDM_CROS_SHIFT (21U) 256 #define DBG_CENSIRQ_ST_IDM_CROS_WIDTH (1U) 257 #define DBG_CENSIRQ_ST_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_ST_IDM_CROS_SHIFT)) & DBG_CENSIRQ_ST_IDM_CROS_MASK) 258 259 #define DBG_CENSIRQ_VLD_ADR_ERR_MASK (0x400000U) 260 #define DBG_CENSIRQ_VLD_ADR_ERR_SHIFT (22U) 261 #define DBG_CENSIRQ_VLD_ADR_ERR_WIDTH (1U) 262 #define DBG_CENSIRQ_VLD_ADR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_VLD_ADR_ERR_SHIFT)) & DBG_CENSIRQ_VLD_ADR_ERR_MASK) 263 264 #define DBG_CENSIRQ_VST_ADR_ERR_MASK (0x800000U) 265 #define DBG_CENSIRQ_VST_ADR_ERR_SHIFT (23U) 266 #define DBG_CENSIRQ_VST_ADR_ERR_WIDTH (1U) 267 #define DBG_CENSIRQ_VST_ADR_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_VST_ADR_ERR_SHIFT)) & DBG_CENSIRQ_VST_ADR_ERR_MASK) 268 269 #define DBG_CENSIRQ_HIST_IDM_CROS_MASK (0x1000000U) 270 #define DBG_CENSIRQ_HIST_IDM_CROS_SHIFT (24U) 271 #define DBG_CENSIRQ_HIST_IDM_CROS_WIDTH (1U) 272 #define DBG_CENSIRQ_HIST_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_HIST_IDM_CROS_SHIFT)) & DBG_CENSIRQ_HIST_IDM_CROS_MASK) 273 /*! @} */ 274 275 /*! @name CENSIRQ2 - Critical Errors Interrupt 2 Register */ 276 /*! @{ */ 277 278 #define DBG_CENSIRQ2_DDMA_ERR_ACC_MASK (0x2U) 279 #define DBG_CENSIRQ2_DDMA_ERR_ACC_SHIFT (1U) 280 #define DBG_CENSIRQ2_DDMA_ERR_ACC_WIDTH (1U) 281 #define DBG_CENSIRQ2_DDMA_ERR_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_DDMA_ERR_ACC_SHIFT)) & DBG_CENSIRQ2_DDMA_ERR_ACC_MASK) 282 283 #define DBG_CENSIRQ2_QMAN_ERR_ACC_MASK (0x4U) 284 #define DBG_CENSIRQ2_QMAN_ERR_ACC_SHIFT (2U) 285 #define DBG_CENSIRQ2_QMAN_ERR_ACC_WIDTH (1U) 286 #define DBG_CENSIRQ2_QMAN_ERR_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_QMAN_ERR_ACC_SHIFT)) & DBG_CENSIRQ2_QMAN_ERR_ACC_MASK) 287 288 #define DBG_CENSIRQ2_QMAN_IDM_CROS_MASK (0x8U) 289 #define DBG_CENSIRQ2_QMAN_IDM_CROS_SHIFT (3U) 290 #define DBG_CENSIRQ2_QMAN_IDM_CROS_WIDTH (1U) 291 #define DBG_CENSIRQ2_QMAN_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_QMAN_IDM_CROS_SHIFT)) & DBG_CENSIRQ2_QMAN_IDM_CROS_MASK) 292 293 #define DBG_CENSIRQ2_DDMA_RG_CROS_MASK (0x80U) 294 #define DBG_CENSIRQ2_DDMA_RG_CROS_SHIFT (7U) 295 #define DBG_CENSIRQ2_DDMA_RG_CROS_WIDTH (1U) 296 #define DBG_CENSIRQ2_DDMA_RG_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_DDMA_RG_CROS_SHIFT)) & DBG_CENSIRQ2_DDMA_RG_CROS_MASK) 297 298 #define DBG_CENSIRQ2_DDMA_IDM_CROS_MASK (0x100U) 299 #define DBG_CENSIRQ2_DDMA_IDM_CROS_SHIFT (8U) 300 #define DBG_CENSIRQ2_DDMA_IDM_CROS_WIDTH (1U) 301 #define DBG_CENSIRQ2_DDMA_IDM_CROS(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_DDMA_IDM_CROS_SHIFT)) & DBG_CENSIRQ2_DDMA_IDM_CROS_MASK) 302 303 #define DBG_CENSIRQ2_ER_IOP_MASK (0x400U) 304 #define DBG_CENSIRQ2_ER_IOP_SHIFT (10U) 305 #define DBG_CENSIRQ2_ER_IOP_WIDTH (1U) 306 #define DBG_CENSIRQ2_ER_IOP(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_ER_IOP_SHIFT)) & DBG_CENSIRQ2_ER_IOP_MASK) 307 308 #define DBG_CENSIRQ2_ER_EDP_MASK (0x1000U) 309 #define DBG_CENSIRQ2_ER_EDP_SHIFT (12U) 310 #define DBG_CENSIRQ2_ER_EDP_WIDTH (1U) 311 #define DBG_CENSIRQ2_ER_EDP(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_ER_EDP_SHIFT)) & DBG_CENSIRQ2_ER_EDP_MASK) 312 313 #define DBG_CENSIRQ2_D_UCSERR_MASK (0x40000000U) 314 #define DBG_CENSIRQ2_D_UCSERR_SHIFT (30U) 315 #define DBG_CENSIRQ2_D_UCSERR_WIDTH (1U) 316 #define DBG_CENSIRQ2_D_UCSERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_D_UCSERR_SHIFT)) & DBG_CENSIRQ2_D_UCSERR_MASK) 317 318 #define DBG_CENSIRQ2_P_UCSERR_MASK (0x80000000U) 319 #define DBG_CENSIRQ2_P_UCSERR_SHIFT (31U) 320 #define DBG_CENSIRQ2_P_UCSERR_WIDTH (1U) 321 #define DBG_CENSIRQ2_P_UCSERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_P_UCSERR_SHIFT)) & DBG_CENSIRQ2_P_UCSERR_MASK) 322 /*! @} */ 323 324 /*! @name CWDOGIRQ - Critical Error Interrupt Requests Register */ 325 /*! @{ */ 326 327 #define DBG_CWDOGIRQ_CNSE_MASK (0x1U) 328 #define DBG_CWDOGIRQ_CNSE_SHIFT (0U) 329 #define DBG_CWDOGIRQ_CNSE_WIDTH (1U) 330 #define DBG_CWDOGIRQ_CNSE(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_CNSE_SHIFT)) & DBG_CWDOGIRQ_CNSE_MASK) 331 332 #define DBG_CWDOGIRQ_WDOG_MAX_MASK (0x10000U) 333 #define DBG_CWDOGIRQ_WDOG_MAX_SHIFT (16U) 334 #define DBG_CWDOGIRQ_WDOG_MAX_WIDTH (1U) 335 #define DBG_CWDOGIRQ_WDOG_MAX(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_WDOG_MAX_SHIFT)) & DBG_CWDOGIRQ_WDOG_MAX_MASK) 336 337 #define DBG_CWDOGIRQ_WDOG_MIN_MASK (0x20000U) 338 #define DBG_CWDOGIRQ_WDOG_MIN_SHIFT (17U) 339 #define DBG_CWDOGIRQ_WDOG_MIN_WIDTH (1U) 340 #define DBG_CWDOGIRQ_WDOG_MIN(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_WDOG_MIN_SHIFT)) & DBG_CWDOGIRQ_WDOG_MIN_MASK) 341 342 #define DBG_CWDOGIRQ_ICUWD_MASK (0x100000U) 343 #define DBG_CWDOGIRQ_ICUWD_SHIFT (20U) 344 #define DBG_CWDOGIRQ_ICUWD_WIDTH (1U) 345 #define DBG_CWDOGIRQ_ICUWD(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_ICUWD_SHIFT)) & DBG_CWDOGIRQ_ICUWD_MASK) 346 347 #define DBG_CWDOGIRQ_IOPWDOG_V_MASK (0x20000000U) 348 #define DBG_CWDOGIRQ_IOPWDOG_V_SHIFT (29U) 349 #define DBG_CWDOGIRQ_IOPWDOG_V_WIDTH (1U) 350 #define DBG_CWDOGIRQ_IOPWDOG_V(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_IOPWDOG_V_SHIFT)) & DBG_CWDOGIRQ_IOPWDOG_V_MASK) 351 352 #define DBG_CWDOGIRQ_EDPWDOG_V_MASK (0x40000000U) 353 #define DBG_CWDOGIRQ_EDPWDOG_V_SHIFT (30U) 354 #define DBG_CWDOGIRQ_EDPWDOG_V_WIDTH (1U) 355 #define DBG_CWDOGIRQ_EDPWDOG_V(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_EDPWDOG_V_SHIFT)) & DBG_CWDOGIRQ_EDPWDOG_V_MASK) 356 357 #define DBG_CWDOGIRQ_EPPWDOG_V_MASK (0x80000000U) 358 #define DBG_CWDOGIRQ_EPPWDOG_V_SHIFT (31U) 359 #define DBG_CWDOGIRQ_EPPWDOG_V_WIDTH (1U) 360 #define DBG_CWDOGIRQ_EPPWDOG_V(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_EPPWDOG_V_SHIFT)) & DBG_CWDOGIRQ_EPPWDOG_V_MASK) 361 /*! @} */ 362 363 /*! @name NENSIRQ - Normal Error Interrupt Requests Register */ 364 /*! @{ */ 365 366 #define DBG_NENSIRQ_NNSE_MASK (0x1U) 367 #define DBG_NENSIRQ_NNSE_SHIFT (0U) 368 #define DBG_NENSIRQ_NNSE_WIDTH (1U) 369 #define DBG_NENSIRQ_NNSE(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_NNSE_SHIFT)) & DBG_NENSIRQ_NNSE_MASK) 370 371 #define DBG_NENSIRQ_DIV_0_V_MASK (0x2U) 372 #define DBG_NENSIRQ_DIV_0_V_SHIFT (1U) 373 #define DBG_NENSIRQ_DIV_0_V_WIDTH (1U) 374 #define DBG_NENSIRQ_DIV_0_V(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_DIV_0_V_SHIFT)) & DBG_NENSIRQ_DIV_0_V_MASK) 375 376 #define DBG_NENSIRQ_OVRFLW_EXCPTN_MASK (0x4U) 377 #define DBG_NENSIRQ_OVRFLW_EXCPTN_SHIFT (2U) 378 #define DBG_NENSIRQ_OVRFLW_EXCPTN_WIDTH (1U) 379 #define DBG_NENSIRQ_OVRFLW_EXCPTN(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_OVRFLW_EXCPTN_SHIFT)) & DBG_NENSIRQ_OVRFLW_EXCPTN_MASK) 380 381 #define DBG_NENSIRQ_EDAP_R_OOR_MASK (0x4000U) 382 #define DBG_NENSIRQ_EDAP_R_OOR_SHIFT (14U) 383 #define DBG_NENSIRQ_EDAP_R_OOR_WIDTH (1U) 384 #define DBG_NENSIRQ_EDAP_R_OOR(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_EDAP_R_OOR_SHIFT)) & DBG_NENSIRQ_EDAP_R_OOR_MASK) 385 386 #define DBG_NENSIRQ_EDAP_W_OOR_MASK (0x8000U) 387 #define DBG_NENSIRQ_EDAP_W_OOR_SHIFT (15U) 388 #define DBG_NENSIRQ_EDAP_W_OOR_WIDTH (1U) 389 #define DBG_NENSIRQ_EDAP_W_OOR(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_EDAP_W_OOR_SHIFT)) & DBG_NENSIRQ_EDAP_W_OOR_MASK) 390 391 #define DBG_NENSIRQ_EPP_CF_ERR_MASK (0x40000U) 392 #define DBG_NENSIRQ_EPP_CF_ERR_SHIFT (18U) 393 #define DBG_NENSIRQ_EPP_CF_ERR_WIDTH (1U) 394 #define DBG_NENSIRQ_EPP_CF_ERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_EPP_CF_ERR_SHIFT)) & DBG_NENSIRQ_EPP_CF_ERR_MASK) 395 396 #define DBG_NENSIRQ_D_CSERR_MASK (0x40000000U) 397 #define DBG_NENSIRQ_D_CSERR_SHIFT (30U) 398 #define DBG_NENSIRQ_D_CSERR_WIDTH (1U) 399 #define DBG_NENSIRQ_D_CSERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_D_CSERR_SHIFT)) & DBG_NENSIRQ_D_CSERR_MASK) 400 401 #define DBG_NENSIRQ_P_CSERR_MASK (0x80000000U) 402 #define DBG_NENSIRQ_P_CSERR_SHIFT (31U) 403 #define DBG_NENSIRQ_P_CSERR_WIDTH (1U) 404 #define DBG_NENSIRQ_P_CSERR(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_P_CSERR_SHIFT)) & DBG_NENSIRQ_P_CSERR_MASK) 405 /*! @} */ 406 407 /*! @name TIMER_IRQ - Timer Interrupt Source Register */ 408 /*! @{ */ 409 410 #define DBG_TIMER_IRQ_TIMER0_IRQ_MASK (0x1U) 411 #define DBG_TIMER_IRQ_TIMER0_IRQ_SHIFT (0U) 412 #define DBG_TIMER_IRQ_TIMER0_IRQ_WIDTH (1U) 413 #define DBG_TIMER_IRQ_TIMER0_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_TIMER0_IRQ_SHIFT)) & DBG_TIMER_IRQ_TIMER0_IRQ_MASK) 414 415 #define DBG_TIMER_IRQ_TIMER1_IRQ_MASK (0x2U) 416 #define DBG_TIMER_IRQ_TIMER1_IRQ_SHIFT (1U) 417 #define DBG_TIMER_IRQ_TIMER1_IRQ_WIDTH (1U) 418 #define DBG_TIMER_IRQ_TIMER1_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_TIMER1_IRQ_SHIFT)) & DBG_TIMER_IRQ_TIMER1_IRQ_MASK) 419 420 #define DBG_TIMER_IRQ_TIMER2_IRQ_MASK (0x4U) 421 #define DBG_TIMER_IRQ_TIMER2_IRQ_SHIFT (2U) 422 #define DBG_TIMER_IRQ_TIMER2_IRQ_WIDTH (1U) 423 #define DBG_TIMER_IRQ_TIMER2_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_TIMER2_IRQ_SHIFT)) & DBG_TIMER_IRQ_TIMER2_IRQ_MASK) 424 425 #define DBG_TIMER_IRQ_TIMER3_IRQ_MASK (0x8U) 426 #define DBG_TIMER_IRQ_TIMER3_IRQ_SHIFT (3U) 427 #define DBG_TIMER_IRQ_TIMER3_IRQ_WIDTH (1U) 428 #define DBG_TIMER_IRQ_TIMER3_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_TIMER3_IRQ_SHIFT)) & DBG_TIMER_IRQ_TIMER3_IRQ_MASK) 429 /*! @} */ 430 431 /*! @name DMA_IRQ - DMA Interrupt Source Register */ 432 /*! @{ */ 433 434 #define DBG_DMA_IRQ_DDMA_IRQ_MASK (0x1U) 435 #define DBG_DMA_IRQ_DDMA_IRQ_SHIFT (0U) 436 #define DBG_DMA_IRQ_DDMA_IRQ_WIDTH (1U) 437 #define DBG_DMA_IRQ_DDMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_DMA_IRQ_DDMA_IRQ_SHIFT)) & DBG_DMA_IRQ_DDMA_IRQ_MASK) 438 439 #define DBG_DMA_IRQ_PDMA_IRQ_MASK (0x2U) 440 #define DBG_DMA_IRQ_PDMA_IRQ_SHIFT (1U) 441 #define DBG_DMA_IRQ_PDMA_IRQ_WIDTH (1U) 442 #define DBG_DMA_IRQ_PDMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_DMA_IRQ_PDMA_IRQ_SHIFT)) & DBG_DMA_IRQ_PDMA_IRQ_MASK) 443 /*! @} */ 444 445 /*! @name POSCINT - Posted Core Interrupt Register */ 446 /*! @{ */ 447 448 #define DBG_POSCINT_PCINT0EN_MASK (0x1U) 449 #define DBG_POSCINT_PCINT0EN_SHIFT (0U) 450 #define DBG_POSCINT_PCINT0EN_WIDTH (1U) 451 #define DBG_POSCINT_PCINT0EN(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT0EN_SHIFT)) & DBG_POSCINT_PCINT0EN_MASK) 452 453 #define DBG_POSCINT_PCINT1EN_MASK (0x2U) 454 #define DBG_POSCINT_PCINT1EN_SHIFT (1U) 455 #define DBG_POSCINT_PCINT1EN_WIDTH (1U) 456 #define DBG_POSCINT_PCINT1EN(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT1EN_SHIFT)) & DBG_POSCINT_PCINT1EN_MASK) 457 458 #define DBG_POSCINT_PCINT2EN_MASK (0x4U) 459 #define DBG_POSCINT_PCINT2EN_SHIFT (2U) 460 #define DBG_POSCINT_PCINT2EN_WIDTH (1U) 461 #define DBG_POSCINT_PCINT2EN(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT2EN_SHIFT)) & DBG_POSCINT_PCINT2EN_MASK) 462 463 #define DBG_POSCINT_PCINT3EN_MASK (0x8U) 464 #define DBG_POSCINT_PCINT3EN_SHIFT (3U) 465 #define DBG_POSCINT_PCINT3EN_WIDTH (1U) 466 #define DBG_POSCINT_PCINT3EN(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT3EN_SHIFT)) & DBG_POSCINT_PCINT3EN_MASK) 467 468 #define DBG_POSCINT_PCINT0ST_MASK (0x100U) 469 #define DBG_POSCINT_PCINT0ST_SHIFT (8U) 470 #define DBG_POSCINT_PCINT0ST_WIDTH (1U) 471 #define DBG_POSCINT_PCINT0ST(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT0ST_SHIFT)) & DBG_POSCINT_PCINT0ST_MASK) 472 473 #define DBG_POSCINT_PCINT1ST_MASK (0x200U) 474 #define DBG_POSCINT_PCINT1ST_SHIFT (9U) 475 #define DBG_POSCINT_PCINT1ST_WIDTH (1U) 476 #define DBG_POSCINT_PCINT1ST(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT1ST_SHIFT)) & DBG_POSCINT_PCINT1ST_MASK) 477 478 #define DBG_POSCINT_PCINT2ST_MASK (0x400U) 479 #define DBG_POSCINT_PCINT2ST_SHIFT (10U) 480 #define DBG_POSCINT_PCINT2ST_WIDTH (1U) 481 #define DBG_POSCINT_PCINT2ST(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT2ST_SHIFT)) & DBG_POSCINT_PCINT2ST_MASK) 482 483 #define DBG_POSCINT_PCINT3ST_MASK (0x800U) 484 #define DBG_POSCINT_PCINT3ST_SHIFT (11U) 485 #define DBG_POSCINT_PCINT3ST_WIDTH (1U) 486 #define DBG_POSCINT_PCINT3ST(x) (((uint32_t)(((uint32_t)(x)) << DBG_POSCINT_PCINT3ST_SHIFT)) & DBG_POSCINT_PCINT3ST_MASK) 487 /*! @} */ 488 489 /*! @name NQBIRQ - Normal QMAN and Buffers Interrupt Register */ 490 /*! @{ */ 491 492 #define DBG_NQBIRQ_NQBIRQ_MASK (0x1U) 493 #define DBG_NQBIRQ_NQBIRQ_SHIFT (0U) 494 #define DBG_NQBIRQ_NQBIRQ_WIDTH (1U) 495 #define DBG_NQBIRQ_NQBIRQ(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_NQBIRQ_SHIFT)) & DBG_NQBIRQ_NQBIRQ_MASK) 496 497 #define DBG_NQBIRQ_QMAN_IRQ_STATUS_MASK (0x2U) 498 #define DBG_NQBIRQ_QMAN_IRQ_STATUS_SHIFT (1U) 499 #define DBG_NQBIRQ_QMAN_IRQ_STATUS_WIDTH (1U) 500 #define DBG_NQBIRQ_QMAN_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_QMAN_IRQ_STATUS_SHIFT)) & DBG_NQBIRQ_QMAN_IRQ_STATUS_MASK) 501 502 #define DBG_NQBIRQ_QMAN_QFULL_MASK (0x4U) 503 #define DBG_NQBIRQ_QMAN_QFULL_SHIFT (2U) 504 #define DBG_NQBIRQ_QMAN_QFULL_WIDTH (1U) 505 #define DBG_NQBIRQ_QMAN_QFULL(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_QMAN_QFULL_SHIFT)) & DBG_NQBIRQ_QMAN_QFULL_MASK) 506 507 #define DBG_NQBIRQ_SNOOP_CSR0_MASK (0x100U) 508 #define DBG_NQBIRQ_SNOOP_CSR0_SHIFT (8U) 509 #define DBG_NQBIRQ_SNOOP_CSR0_WIDTH (1U) 510 #define DBG_NQBIRQ_SNOOP_CSR0(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_SNOOP_CSR0_SHIFT)) & DBG_NQBIRQ_SNOOP_CSR0_MASK) 511 512 #define DBG_NQBIRQ_SNOOP_CSR1_MASK (0x200U) 513 #define DBG_NQBIRQ_SNOOP_CSR1_SHIFT (9U) 514 #define DBG_NQBIRQ_SNOOP_CSR1_WIDTH (1U) 515 #define DBG_NQBIRQ_SNOOP_CSR1(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_SNOOP_CSR1_SHIFT)) & DBG_NQBIRQ_SNOOP_CSR1_MASK) 516 /*! @} */ 517 518 /*! @name NENSIRQ_M - Normal Error Interrupt Request Mask Register */ 519 /*! @{ */ 520 521 #define DBG_NENSIRQ_M_NNSE_M_MASK (0x1U) 522 #define DBG_NENSIRQ_M_NNSE_M_SHIFT (0U) 523 #define DBG_NENSIRQ_M_NNSE_M_WIDTH (1U) 524 #define DBG_NENSIRQ_M_NNSE_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_NNSE_M_SHIFT)) & DBG_NENSIRQ_M_NNSE_M_MASK) 525 526 #define DBG_NENSIRQ_M_DIV_0_V_M_MASK (0x2U) 527 #define DBG_NENSIRQ_M_DIV_0_V_M_SHIFT (1U) 528 #define DBG_NENSIRQ_M_DIV_0_V_M_WIDTH (1U) 529 #define DBG_NENSIRQ_M_DIV_0_V_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_DIV_0_V_M_SHIFT)) & DBG_NENSIRQ_M_DIV_0_V_M_MASK) 530 531 #define DBG_NENSIRQ_M_OVRFLW_EXCPTN_M_MASK (0x4U) 532 #define DBG_NENSIRQ_M_OVRFLW_EXCPTN_M_SHIFT (2U) 533 #define DBG_NENSIRQ_M_OVRFLW_EXCPTN_M_WIDTH (1U) 534 #define DBG_NENSIRQ_M_OVRFLW_EXCPTN_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_OVRFLW_EXCPTN_M_SHIFT)) & DBG_NENSIRQ_M_OVRFLW_EXCPTN_M_MASK) 535 536 #define DBG_NENSIRQ_M_EDAP_R_OOR_M_MASK (0x4000U) 537 #define DBG_NENSIRQ_M_EDAP_R_OOR_M_SHIFT (14U) 538 #define DBG_NENSIRQ_M_EDAP_R_OOR_M_WIDTH (1U) 539 #define DBG_NENSIRQ_M_EDAP_R_OOR_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_EDAP_R_OOR_M_SHIFT)) & DBG_NENSIRQ_M_EDAP_R_OOR_M_MASK) 540 541 #define DBG_NENSIRQ_M_EDAP_W_OOR_M_MASK (0x8000U) 542 #define DBG_NENSIRQ_M_EDAP_W_OOR_M_SHIFT (15U) 543 #define DBG_NENSIRQ_M_EDAP_W_OOR_M_WIDTH (1U) 544 #define DBG_NENSIRQ_M_EDAP_W_OOR_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_EDAP_W_OOR_M_SHIFT)) & DBG_NENSIRQ_M_EDAP_W_OOR_M_MASK) 545 546 #define DBG_NENSIRQ_M_EPP_CF_ERR_M_MASK (0x40000U) 547 #define DBG_NENSIRQ_M_EPP_CF_ERR_M_SHIFT (18U) 548 #define DBG_NENSIRQ_M_EPP_CF_ERR_M_WIDTH (1U) 549 #define DBG_NENSIRQ_M_EPP_CF_ERR_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_M_EPP_CF_ERR_M_SHIFT)) & DBG_NENSIRQ_M_EPP_CF_ERR_M_MASK) 550 /*! @} */ 551 552 /*! @name TIMER_IRQ_M - Timer Interrupt Mask Register */ 553 /*! @{ */ 554 555 #define DBG_TIMER_IRQ_M_TIMER0_MASK_MASK (0x1U) 556 #define DBG_TIMER_IRQ_M_TIMER0_MASK_SHIFT (0U) 557 #define DBG_TIMER_IRQ_M_TIMER0_MASK_WIDTH (1U) 558 #define DBG_TIMER_IRQ_M_TIMER0_MASK(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_M_TIMER0_MASK_SHIFT)) & DBG_TIMER_IRQ_M_TIMER0_MASK_MASK) 559 560 #define DBG_TIMER_IRQ_M_TIMER1_MASK_MASK (0x2U) 561 #define DBG_TIMER_IRQ_M_TIMER1_MASK_SHIFT (1U) 562 #define DBG_TIMER_IRQ_M_TIMER1_MASK_WIDTH (1U) 563 #define DBG_TIMER_IRQ_M_TIMER1_MASK(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_M_TIMER1_MASK_SHIFT)) & DBG_TIMER_IRQ_M_TIMER1_MASK_MASK) 564 565 #define DBG_TIMER_IRQ_M_TIMER2_MASK_MASK (0x4U) 566 #define DBG_TIMER_IRQ_M_TIMER2_MASK_SHIFT (2U) 567 #define DBG_TIMER_IRQ_M_TIMER2_MASK_WIDTH (1U) 568 #define DBG_TIMER_IRQ_M_TIMER2_MASK(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_M_TIMER2_MASK_SHIFT)) & DBG_TIMER_IRQ_M_TIMER2_MASK_MASK) 569 570 #define DBG_TIMER_IRQ_M_TIMER3_MASK_MASK (0x8U) 571 #define DBG_TIMER_IRQ_M_TIMER3_MASK_SHIFT (3U) 572 #define DBG_TIMER_IRQ_M_TIMER3_MASK_WIDTH (1U) 573 #define DBG_TIMER_IRQ_M_TIMER3_MASK(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_M_TIMER3_MASK_SHIFT)) & DBG_TIMER_IRQ_M_TIMER3_MASK_MASK) 574 /*! @} */ 575 576 /*! @name NQBIRQ_M - Normal QMAN and Buffers Interrupt Mask Register */ 577 /*! @{ */ 578 579 #define DBG_NQBIRQ_M_NQBIRQ_M_MASK (0x1U) 580 #define DBG_NQBIRQ_M_NQBIRQ_M_SHIFT (0U) 581 #define DBG_NQBIRQ_M_NQBIRQ_M_WIDTH (1U) 582 #define DBG_NQBIRQ_M_NQBIRQ_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_M_NQBIRQ_M_SHIFT)) & DBG_NQBIRQ_M_NQBIRQ_M_MASK) 583 584 #define DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M_MASK (0x2U) 585 #define DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M_SHIFT (1U) 586 #define DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M_WIDTH (1U) 587 #define DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M_SHIFT)) & DBG_NQBIRQ_M_QMAN_IRQ_STATUS_M_MASK) 588 589 #define DBG_NQBIRQ_M_QMAN_QFULL_M_MASK (0x4U) 590 #define DBG_NQBIRQ_M_QMAN_QFULL_M_SHIFT (2U) 591 #define DBG_NQBIRQ_M_QMAN_QFULL_M_WIDTH (1U) 592 #define DBG_NQBIRQ_M_QMAN_QFULL_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_M_QMAN_QFULL_M_SHIFT)) & DBG_NQBIRQ_M_QMAN_QFULL_M_MASK) 593 594 #define DBG_NQBIRQ_M_SNOOP_CSR0_M_MASK (0x100U) 595 #define DBG_NQBIRQ_M_SNOOP_CSR0_M_SHIFT (8U) 596 #define DBG_NQBIRQ_M_SNOOP_CSR0_M_WIDTH (1U) 597 #define DBG_NQBIRQ_M_SNOOP_CSR0_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_M_SNOOP_CSR0_M_SHIFT)) & DBG_NQBIRQ_M_SNOOP_CSR0_M_MASK) 598 599 #define DBG_NQBIRQ_M_SNOOP_CSR1_M_MASK (0x200U) 600 #define DBG_NQBIRQ_M_SNOOP_CSR1_M_SHIFT (9U) 601 #define DBG_NQBIRQ_M_SNOOP_CSR1_M_WIDTH (1U) 602 #define DBG_NQBIRQ_M_SNOOP_CSR1_M(x) (((uint32_t)(((uint32_t)(x)) << DBG_NQBIRQ_M_SNOOP_CSR1_M_SHIFT)) & DBG_NQBIRQ_M_SNOOP_CSR1_M_MASK) 603 /*! @} */ 604 605 /*! @name DBG_STACK_START - Stack Violation Start Address Register */ 606 /*! @{ */ 607 608 #define DBG_DBG_STACK_START_STK_VIOLTN_START_ADD_MASK (0xFFFFFFFFU) 609 #define DBG_DBG_STACK_START_STK_VIOLTN_START_ADD_SHIFT (0U) 610 #define DBG_DBG_STACK_START_STK_VIOLTN_START_ADD_WIDTH (32U) 611 #define DBG_DBG_STACK_START_STK_VIOLTN_START_ADD(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_STACK_START_STK_VIOLTN_START_ADD_SHIFT)) & DBG_DBG_STACK_START_STK_VIOLTN_START_ADD_MASK) 612 /*! @} */ 613 614 /*! @name DBG_STACK_END - Stack Violation End Address Register */ 615 /*! @{ */ 616 617 #define DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD_MASK (0xFFFFFFFFU) 618 #define DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD_SHIFT (0U) 619 #define DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD_WIDTH (32U) 620 #define DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD_SHIFT)) & DBG_DBG_STACK_END_STACK_VIOLTN_END_ADD_MASK) 621 /*! @} */ 622 623 /*! @name DBG_DUNMPD_MSK - DBG DMSS Unmapped Access Mask Register */ 624 /*! @{ */ 625 626 #define DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK_MASK (0xFFFFFFFFU) 627 #define DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK_SHIFT (0U) 628 #define DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK_WIDTH (32U) 629 #define DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK_SHIFT)) & DBG_DBG_DUNMPD_MSK_DEXCPTN_UNMAPD_MASK_MASK) 630 /*! @} */ 631 632 /*! @name DBG_DUNMPD - DMSS Unmapped Access Status Register */ 633 /*! @{ */ 634 635 #define DBG_DBG_DUNMPD_DEXCPTN_UNMAPD_MASK (0xFFFFFFFFU) 636 #define DBG_DBG_DUNMPD_DEXCPTN_UNMAPD_SHIFT (0U) 637 #define DBG_DBG_DUNMPD_DEXCPTN_UNMAPD_WIDTH (32U) 638 #define DBG_DBG_DUNMPD_DEXCPTN_UNMAPD(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DUNMPD_DEXCPTN_UNMAPD_SHIFT)) & DBG_DBG_DUNMPD_DEXCPTN_UNMAPD_MASK) 639 /*! @} */ 640 641 /*! @name CENSIRQ_S - Critical Error Interrupt Request Shadow Register */ 642 /*! @{ */ 643 644 #define DBG_CENSIRQ_S_CNSIPV_S_MASK (0x2U) 645 #define DBG_CENSIRQ_S_CNSIPV_S_SHIFT (1U) 646 #define DBG_CENSIRQ_S_CNSIPV_S_WIDTH (1U) 647 #define DBG_CENSIRQ_S_CNSIPV_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_CNSIPV_S_SHIFT)) & DBG_CENSIRQ_S_CNSIPV_S_MASK) 648 649 #define DBG_CENSIRQ_S_CNSILOP_S_MASK (0x4U) 650 #define DBG_CENSIRQ_S_CNSILOP_S_SHIFT (2U) 651 #define DBG_CENSIRQ_S_CNSILOP_S_WIDTH (1U) 652 #define DBG_CENSIRQ_S_CNSILOP_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_CNSILOP_S_SHIFT)) & DBG_CENSIRQ_S_CNSILOP_S_MASK) 653 654 #define DBG_CENSIRQ_S_CNSIRE_S_MASK (0x10U) 655 #define DBG_CENSIRQ_S_CNSIRE_S_SHIFT (4U) 656 #define DBG_CENSIRQ_S_CNSIRE_S_WIDTH (1U) 657 #define DBG_CENSIRQ_S_CNSIRE_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_CNSIRE_S_SHIFT)) & DBG_CENSIRQ_S_CNSIRE_S_MASK) 658 659 #define DBG_CENSIRQ_S_IN_PRIV_S_MASK (0x100U) 660 #define DBG_CENSIRQ_S_IN_PRIV_S_SHIFT (8U) 661 #define DBG_CENSIRQ_S_IN_PRIV_S_WIDTH (1U) 662 #define DBG_CENSIRQ_S_IN_PRIV_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_IN_PRIV_S_SHIFT)) & DBG_CENSIRQ_S_IN_PRIV_S_MASK) 663 664 #define DBG_CENSIRQ_S_OUT_PRIV_S_MASK (0x200U) 665 #define DBG_CENSIRQ_S_OUT_PRIV_S_SHIFT (9U) 666 #define DBG_CENSIRQ_S_OUT_PRIV_S_WIDTH (1U) 667 #define DBG_CENSIRQ_S_OUT_PRIV_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_OUT_PRIV_S_SHIFT)) & DBG_CENSIRQ_S_OUT_PRIV_S_MASK) 668 669 #define DBG_CENSIRQ_S_LD_PRIV_ACC_S_MASK (0x400U) 670 #define DBG_CENSIRQ_S_LD_PRIV_ACC_S_SHIFT (10U) 671 #define DBG_CENSIRQ_S_LD_PRIV_ACC_S_WIDTH (1U) 672 #define DBG_CENSIRQ_S_LD_PRIV_ACC_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_LD_PRIV_ACC_S_SHIFT)) & DBG_CENSIRQ_S_LD_PRIV_ACC_S_MASK) 673 674 #define DBG_CENSIRQ_S_ST_PRIV_ACC_S_MASK (0x800U) 675 #define DBG_CENSIRQ_S_ST_PRIV_ACC_S_SHIFT (11U) 676 #define DBG_CENSIRQ_S_ST_PRIV_ACC_S_WIDTH (1U) 677 #define DBG_CENSIRQ_S_ST_PRIV_ACC_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_ST_PRIV_ACC_S_SHIFT)) & DBG_CENSIRQ_S_ST_PRIV_ACC_S_MASK) 678 679 #define DBG_CENSIRQ_S_LD_BLANK_ACC_S_MASK (0x1000U) 680 #define DBG_CENSIRQ_S_LD_BLANK_ACC_S_SHIFT (12U) 681 #define DBG_CENSIRQ_S_LD_BLANK_ACC_S_WIDTH (1U) 682 #define DBG_CENSIRQ_S_LD_BLANK_ACC_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_LD_BLANK_ACC_S_SHIFT)) & DBG_CENSIRQ_S_LD_BLANK_ACC_S_MASK) 683 684 #define DBG_CENSIRQ_S_ST_BLANK_ACC_S_MASK (0x2000U) 685 #define DBG_CENSIRQ_S_ST_BLANK_ACC_S_SHIFT (13U) 686 #define DBG_CENSIRQ_S_ST_BLANK_ACC_S_WIDTH (1U) 687 #define DBG_CENSIRQ_S_ST_BLANK_ACC_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_ST_BLANK_ACC_S_SHIFT)) & DBG_CENSIRQ_S_ST_BLANK_ACC_S_MASK) 688 689 #define DBG_CENSIRQ_S_LD_RG_CROS_S_MASK (0x4000U) 690 #define DBG_CENSIRQ_S_LD_RG_CROS_S_SHIFT (14U) 691 #define DBG_CENSIRQ_S_LD_RG_CROS_S_WIDTH (1U) 692 #define DBG_CENSIRQ_S_LD_RG_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_LD_RG_CROS_S_SHIFT)) & DBG_CENSIRQ_S_LD_RG_CROS_S_MASK) 693 694 #define DBG_CENSIRQ_S_ST_RG_CROS_S_MASK (0x8000U) 695 #define DBG_CENSIRQ_S_ST_RG_CROS_S_SHIFT (15U) 696 #define DBG_CENSIRQ_S_ST_RG_CROS_S_WIDTH (1U) 697 #define DBG_CENSIRQ_S_ST_RG_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_ST_RG_CROS_S_SHIFT)) & DBG_CENSIRQ_S_ST_RG_CROS_S_MASK) 698 699 #define DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S_MASK (0x20000U) 700 #define DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S_SHIFT (17U) 701 #define DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S_WIDTH (1U) 702 #define DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S_SHIFT)) & DBG_CENSIRQ_S_STACK_VIOL_EXCPTN_S_MASK) 703 704 #define DBG_CENSIRQ_S_EXC_E_S_MASK (0x40000U) 705 #define DBG_CENSIRQ_S_EXC_E_S_SHIFT (18U) 706 #define DBG_CENSIRQ_S_EXC_E_S_WIDTH (1U) 707 #define DBG_CENSIRQ_S_EXC_E_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_EXC_E_S_SHIFT)) & DBG_CENSIRQ_S_EXC_E_S_MASK) 708 709 #define DBG_CENSIRQ_S_ER_EXOK_S_MASK (0x80000U) 710 #define DBG_CENSIRQ_S_ER_EXOK_S_SHIFT (19U) 711 #define DBG_CENSIRQ_S_ER_EXOK_S_WIDTH (1U) 712 #define DBG_CENSIRQ_S_ER_EXOK_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_ER_EXOK_S_SHIFT)) & DBG_CENSIRQ_S_ER_EXOK_S_MASK) 713 714 #define DBG_CENSIRQ_S_LD_IDM_CROS_S_MASK (0x100000U) 715 #define DBG_CENSIRQ_S_LD_IDM_CROS_S_SHIFT (20U) 716 #define DBG_CENSIRQ_S_LD_IDM_CROS_S_WIDTH (1U) 717 #define DBG_CENSIRQ_S_LD_IDM_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_LD_IDM_CROS_S_SHIFT)) & DBG_CENSIRQ_S_LD_IDM_CROS_S_MASK) 718 719 #define DBG_CENSIRQ_S_ST_IDM_CROS_S_MASK (0x200000U) 720 #define DBG_CENSIRQ_S_ST_IDM_CROS_S_SHIFT (21U) 721 #define DBG_CENSIRQ_S_ST_IDM_CROS_S_WIDTH (1U) 722 #define DBG_CENSIRQ_S_ST_IDM_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_ST_IDM_CROS_S_SHIFT)) & DBG_CENSIRQ_S_ST_IDM_CROS_S_MASK) 723 724 #define DBG_CENSIRQ_S_VLD_ADR_ERR_S_MASK (0x400000U) 725 #define DBG_CENSIRQ_S_VLD_ADR_ERR_S_SHIFT (22U) 726 #define DBG_CENSIRQ_S_VLD_ADR_ERR_S_WIDTH (1U) 727 #define DBG_CENSIRQ_S_VLD_ADR_ERR_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_VLD_ADR_ERR_S_SHIFT)) & DBG_CENSIRQ_S_VLD_ADR_ERR_S_MASK) 728 729 #define DBG_CENSIRQ_S_VST_ADR_ERR_S_MASK (0x800000U) 730 #define DBG_CENSIRQ_S_VST_ADR_ERR_S_SHIFT (23U) 731 #define DBG_CENSIRQ_S_VST_ADR_ERR_S_WIDTH (1U) 732 #define DBG_CENSIRQ_S_VST_ADR_ERR_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_VST_ADR_ERR_S_SHIFT)) & DBG_CENSIRQ_S_VST_ADR_ERR_S_MASK) 733 734 #define DBG_CENSIRQ_S_HIST_IDM_CROS_S_MASK (0x1000000U) 735 #define DBG_CENSIRQ_S_HIST_IDM_CROS_S_SHIFT (24U) 736 #define DBG_CENSIRQ_S_HIST_IDM_CROS_S_WIDTH (1U) 737 #define DBG_CENSIRQ_S_HIST_IDM_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ_S_HIST_IDM_CROS_S_SHIFT)) & DBG_CENSIRQ_S_HIST_IDM_CROS_S_MASK) 738 /*! @} */ 739 740 /*! @name CENSIRQ2_S - Critical Error Interrupt Request 2 Shadow Register */ 741 /*! @{ */ 742 743 #define DBG_CENSIRQ2_S_DDMA_RG_CROS_S_MASK (0x80U) 744 #define DBG_CENSIRQ2_S_DDMA_RG_CROS_S_SHIFT (7U) 745 #define DBG_CENSIRQ2_S_DDMA_RG_CROS_S_WIDTH (1U) 746 #define DBG_CENSIRQ2_S_DDMA_RG_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_S_DDMA_RG_CROS_S_SHIFT)) & DBG_CENSIRQ2_S_DDMA_RG_CROS_S_MASK) 747 748 #define DBG_CENSIRQ2_S_DDMA_IDM_CROS_S_MASK (0x100U) 749 #define DBG_CENSIRQ2_S_DDMA_IDM_CROS_S_SHIFT (8U) 750 #define DBG_CENSIRQ2_S_DDMA_IDM_CROS_S_WIDTH (1U) 751 #define DBG_CENSIRQ2_S_DDMA_IDM_CROS_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_S_DDMA_IDM_CROS_S_SHIFT)) & DBG_CENSIRQ2_S_DDMA_IDM_CROS_S_MASK) 752 753 #define DBG_CENSIRQ2_S_ER_IOP_S_MASK (0x400U) 754 #define DBG_CENSIRQ2_S_ER_IOP_S_SHIFT (10U) 755 #define DBG_CENSIRQ2_S_ER_IOP_S_WIDTH (1U) 756 #define DBG_CENSIRQ2_S_ER_IOP_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_S_ER_IOP_S_SHIFT)) & DBG_CENSIRQ2_S_ER_IOP_S_MASK) 757 758 #define DBG_CENSIRQ2_S_ER_EPP_S_MASK (0x800U) 759 #define DBG_CENSIRQ2_S_ER_EPP_S_SHIFT (11U) 760 #define DBG_CENSIRQ2_S_ER_EPP_S_WIDTH (1U) 761 #define DBG_CENSIRQ2_S_ER_EPP_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_S_ER_EPP_S_SHIFT)) & DBG_CENSIRQ2_S_ER_EPP_S_MASK) 762 763 #define DBG_CENSIRQ2_S_ER_EDP_S_MASK (0x1000U) 764 #define DBG_CENSIRQ2_S_ER_EDP_S_SHIFT (12U) 765 #define DBG_CENSIRQ2_S_ER_EDP_S_WIDTH (1U) 766 #define DBG_CENSIRQ2_S_ER_EDP_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CENSIRQ2_S_ER_EDP_S_SHIFT)) & DBG_CENSIRQ2_S_ER_EDP_S_MASK) 767 /*! @} */ 768 769 /*! @name CWDOGIRQ_S - Critical Error Interrupt Request Shadow Register */ 770 /*! @{ */ 771 772 #define DBG_CWDOGIRQ_S_WDOG_MAX_S_MASK (0x10000U) 773 #define DBG_CWDOGIRQ_S_WDOG_MAX_S_SHIFT (16U) 774 #define DBG_CWDOGIRQ_S_WDOG_MAX_S_WIDTH (1U) 775 #define DBG_CWDOGIRQ_S_WDOG_MAX_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_WDOG_MAX_S_SHIFT)) & DBG_CWDOGIRQ_S_WDOG_MAX_S_MASK) 776 777 #define DBG_CWDOGIRQ_S_WDOG_MIN_S_MASK (0x20000U) 778 #define DBG_CWDOGIRQ_S_WDOG_MIN_S_SHIFT (17U) 779 #define DBG_CWDOGIRQ_S_WDOG_MIN_S_WIDTH (1U) 780 #define DBG_CWDOGIRQ_S_WDOG_MIN_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_WDOG_MIN_S_SHIFT)) & DBG_CWDOGIRQ_S_WDOG_MIN_S_MASK) 781 782 #define DBG_CWDOGIRQ_S_ICUWD_S_MASK (0x100000U) 783 #define DBG_CWDOGIRQ_S_ICUWD_S_SHIFT (20U) 784 #define DBG_CWDOGIRQ_S_ICUWD_S_WIDTH (1U) 785 #define DBG_CWDOGIRQ_S_ICUWD_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_ICUWD_S_SHIFT)) & DBG_CWDOGIRQ_S_ICUWD_S_MASK) 786 787 #define DBG_CWDOGIRQ_S_IOPWDOG_V_S_MASK (0x20000000U) 788 #define DBG_CWDOGIRQ_S_IOPWDOG_V_S_SHIFT (29U) 789 #define DBG_CWDOGIRQ_S_IOPWDOG_V_S_WIDTH (1U) 790 #define DBG_CWDOGIRQ_S_IOPWDOG_V_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_IOPWDOG_V_S_SHIFT)) & DBG_CWDOGIRQ_S_IOPWDOG_V_S_MASK) 791 792 #define DBG_CWDOGIRQ_S_EDPWDOG_V_S_MASK (0x40000000U) 793 #define DBG_CWDOGIRQ_S_EDPWDOG_V_S_SHIFT (30U) 794 #define DBG_CWDOGIRQ_S_EDPWDOG_V_S_WIDTH (1U) 795 #define DBG_CWDOGIRQ_S_EDPWDOG_V_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_EDPWDOG_V_S_SHIFT)) & DBG_CWDOGIRQ_S_EDPWDOG_V_S_MASK) 796 797 #define DBG_CWDOGIRQ_S_EPPWDOG_V_S_MASK (0x80000000U) 798 #define DBG_CWDOGIRQ_S_EPPWDOG_V_S_SHIFT (31U) 799 #define DBG_CWDOGIRQ_S_EPPWDOG_V_S_WIDTH (1U) 800 #define DBG_CWDOGIRQ_S_EPPWDOG_V_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_CWDOGIRQ_S_EPPWDOG_V_S_SHIFT)) & DBG_CWDOGIRQ_S_EPPWDOG_V_S_MASK) 801 /*! @} */ 802 803 /*! @name NENSIRQ_S - Normal Error Interrupt Requests Shadow Register */ 804 /*! @{ */ 805 806 #define DBG_NENSIRQ_S_DIV_0_V_S_MASK (0x2U) 807 #define DBG_NENSIRQ_S_DIV_0_V_S_SHIFT (1U) 808 #define DBG_NENSIRQ_S_DIV_0_V_S_WIDTH (1U) 809 #define DBG_NENSIRQ_S_DIV_0_V_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_S_DIV_0_V_S_SHIFT)) & DBG_NENSIRQ_S_DIV_0_V_S_MASK) 810 811 #define DBG_NENSIRQ_S_OVRFLW_EXCPTN_S_MASK (0x4U) 812 #define DBG_NENSIRQ_S_OVRFLW_EXCPTN_S_SHIFT (2U) 813 #define DBG_NENSIRQ_S_OVRFLW_EXCPTN_S_WIDTH (1U) 814 #define DBG_NENSIRQ_S_OVRFLW_EXCPTN_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_S_OVRFLW_EXCPTN_S_SHIFT)) & DBG_NENSIRQ_S_OVRFLW_EXCPTN_S_MASK) 815 816 #define DBG_NENSIRQ_S_EDAP_R_OOR_S_MASK (0x4000U) 817 #define DBG_NENSIRQ_S_EDAP_R_OOR_S_SHIFT (14U) 818 #define DBG_NENSIRQ_S_EDAP_R_OOR_S_WIDTH (1U) 819 #define DBG_NENSIRQ_S_EDAP_R_OOR_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_S_EDAP_R_OOR_S_SHIFT)) & DBG_NENSIRQ_S_EDAP_R_OOR_S_MASK) 820 821 #define DBG_NENSIRQ_S_EDAP_W_OOR_S_MASK (0x8000U) 822 #define DBG_NENSIRQ_S_EDAP_W_OOR_S_SHIFT (15U) 823 #define DBG_NENSIRQ_S_EDAP_W_OOR_S_WIDTH (1U) 824 #define DBG_NENSIRQ_S_EDAP_W_OOR_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_S_EDAP_W_OOR_S_SHIFT)) & DBG_NENSIRQ_S_EDAP_W_OOR_S_MASK) 825 826 #define DBG_NENSIRQ_S_EPP_CF_ERR_S_MASK (0x40000U) 827 #define DBG_NENSIRQ_S_EPP_CF_ERR_S_SHIFT (18U) 828 #define DBG_NENSIRQ_S_EPP_CF_ERR_S_WIDTH (1U) 829 #define DBG_NENSIRQ_S_EPP_CF_ERR_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_NENSIRQ_S_EPP_CF_ERR_S_SHIFT)) & DBG_NENSIRQ_S_EPP_CF_ERR_S_MASK) 830 /*! @} */ 831 832 /*! @name TIMER_IRQ_S - Timer Interrupt Shadow Register */ 833 /*! @{ */ 834 835 #define DBG_TIMER_IRQ_S_TIMER0_IRQ_S_MASK (0x1U) 836 #define DBG_TIMER_IRQ_S_TIMER0_IRQ_S_SHIFT (0U) 837 #define DBG_TIMER_IRQ_S_TIMER0_IRQ_S_WIDTH (1U) 838 #define DBG_TIMER_IRQ_S_TIMER0_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_S_TIMER0_IRQ_S_SHIFT)) & DBG_TIMER_IRQ_S_TIMER0_IRQ_S_MASK) 839 840 #define DBG_TIMER_IRQ_S_TIMER1_IRQ_S_MASK (0x2U) 841 #define DBG_TIMER_IRQ_S_TIMER1_IRQ_S_SHIFT (1U) 842 #define DBG_TIMER_IRQ_S_TIMER1_IRQ_S_WIDTH (1U) 843 #define DBG_TIMER_IRQ_S_TIMER1_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_S_TIMER1_IRQ_S_SHIFT)) & DBG_TIMER_IRQ_S_TIMER1_IRQ_S_MASK) 844 845 #define DBG_TIMER_IRQ_S_TIMER2_IRQ_S_MASK (0x4U) 846 #define DBG_TIMER_IRQ_S_TIMER2_IRQ_S_SHIFT (2U) 847 #define DBG_TIMER_IRQ_S_TIMER2_IRQ_S_WIDTH (1U) 848 #define DBG_TIMER_IRQ_S_TIMER2_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_S_TIMER2_IRQ_S_SHIFT)) & DBG_TIMER_IRQ_S_TIMER2_IRQ_S_MASK) 849 850 #define DBG_TIMER_IRQ_S_TIMER3_IRQ_S_MASK (0x8U) 851 #define DBG_TIMER_IRQ_S_TIMER3_IRQ_S_SHIFT (3U) 852 #define DBG_TIMER_IRQ_S_TIMER3_IRQ_S_WIDTH (1U) 853 #define DBG_TIMER_IRQ_S_TIMER3_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_TIMER_IRQ_S_TIMER3_IRQ_S_SHIFT)) & DBG_TIMER_IRQ_S_TIMER3_IRQ_S_MASK) 854 /*! @} */ 855 856 /*! @name DMA_IRQ_S - DMA Interrupt Shadow Register */ 857 /*! @{ */ 858 859 #define DBG_DMA_IRQ_S_DDMA_IRQ_S_MASK (0x1U) 860 #define DBG_DMA_IRQ_S_DDMA_IRQ_S_SHIFT (0U) 861 #define DBG_DMA_IRQ_S_DDMA_IRQ_S_WIDTH (1U) 862 #define DBG_DMA_IRQ_S_DDMA_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_DMA_IRQ_S_DDMA_IRQ_S_SHIFT)) & DBG_DMA_IRQ_S_DDMA_IRQ_S_MASK) 863 864 #define DBG_DMA_IRQ_S_PDMA_IRQ_S_MASK (0x2U) 865 #define DBG_DMA_IRQ_S_PDMA_IRQ_S_SHIFT (1U) 866 #define DBG_DMA_IRQ_S_PDMA_IRQ_S_WIDTH (1U) 867 #define DBG_DMA_IRQ_S_PDMA_IRQ_S(x) (((uint32_t)(((uint32_t)(x)) << DBG_DMA_IRQ_S_PDMA_IRQ_S_SHIFT)) & DBG_DMA_IRQ_S_PDMA_IRQ_S_MASK) 868 /*! @} */ 869 870 /*! @name DBG_DESC_ID - DBG DESC ID Register */ 871 /*! @{ */ 872 873 #define DBG_DBG_DESC_ID_Q0_BLANK_ACC_MASK (0x1U) 874 #define DBG_DBG_DESC_ID_Q0_BLANK_ACC_SHIFT (0U) 875 #define DBG_DBG_DESC_ID_Q0_BLANK_ACC_WIDTH (1U) 876 #define DBG_DBG_DESC_ID_Q0_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DESC_ID_Q0_BLANK_ACC_SHIFT)) & DBG_DBG_DESC_ID_Q0_BLANK_ACC_MASK) 877 878 #define DBG_DBG_DESC_ID_Q1_BLANK_ACC_MASK (0x2U) 879 #define DBG_DBG_DESC_ID_Q1_BLANK_ACC_SHIFT (1U) 880 #define DBG_DBG_DESC_ID_Q1_BLANK_ACC_WIDTH (1U) 881 #define DBG_DBG_DESC_ID_Q1_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DESC_ID_Q1_BLANK_ACC_SHIFT)) & DBG_DBG_DESC_ID_Q1_BLANK_ACC_MASK) 882 883 #define DBG_DBG_DESC_ID_Q2_BLANK_ACC_MASK (0x4U) 884 #define DBG_DBG_DESC_ID_Q2_BLANK_ACC_SHIFT (2U) 885 #define DBG_DBG_DESC_ID_Q2_BLANK_ACC_WIDTH (1U) 886 #define DBG_DBG_DESC_ID_Q2_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DESC_ID_Q2_BLANK_ACC_SHIFT)) & DBG_DBG_DESC_ID_Q2_BLANK_ACC_MASK) 887 888 #define DBG_DBG_DESC_ID_Q3_BLANK_ACC_MASK (0x8U) 889 #define DBG_DBG_DESC_ID_Q3_BLANK_ACC_SHIFT (3U) 890 #define DBG_DBG_DESC_ID_Q3_BLANK_ACC_WIDTH (1U) 891 #define DBG_DBG_DESC_ID_Q3_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DESC_ID_Q3_BLANK_ACC_SHIFT)) & DBG_DBG_DESC_ID_Q3_BLANK_ACC_MASK) 892 893 #define DBG_DBG_DESC_ID_MSTR_BLANK_ACC_MASK (0x10000U) 894 #define DBG_DBG_DESC_ID_MSTR_BLANK_ACC_SHIFT (16U) 895 #define DBG_DBG_DESC_ID_MSTR_BLANK_ACC_WIDTH (1U) 896 #define DBG_DBG_DESC_ID_MSTR_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_DESC_ID_MSTR_BLANK_ACC_SHIFT)) & DBG_DBG_DESC_ID_MSTR_BLANK_ACC_MASK) 897 /*! @} */ 898 899 /*! @name DBG_QMAN_ID - DBG QMAN ID Register */ 900 /*! @{ */ 901 902 #define DBG_DBG_QMAN_ID_Q0_BLANK_ACC_MASK (0x1U) 903 #define DBG_DBG_QMAN_ID_Q0_BLANK_ACC_SHIFT (0U) 904 #define DBG_DBG_QMAN_ID_Q0_BLANK_ACC_WIDTH (1U) 905 #define DBG_DBG_QMAN_ID_Q0_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_QMAN_ID_Q0_BLANK_ACC_SHIFT)) & DBG_DBG_QMAN_ID_Q0_BLANK_ACC_MASK) 906 907 #define DBG_DBG_QMAN_ID_Q1_BLANK_ACC_MASK (0x2U) 908 #define DBG_DBG_QMAN_ID_Q1_BLANK_ACC_SHIFT (1U) 909 #define DBG_DBG_QMAN_ID_Q1_BLANK_ACC_WIDTH (1U) 910 #define DBG_DBG_QMAN_ID_Q1_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_QMAN_ID_Q1_BLANK_ACC_SHIFT)) & DBG_DBG_QMAN_ID_Q1_BLANK_ACC_MASK) 911 912 #define DBG_DBG_QMAN_ID_Q2_BLANK_ACC_MASK (0x4U) 913 #define DBG_DBG_QMAN_ID_Q2_BLANK_ACC_SHIFT (2U) 914 #define DBG_DBG_QMAN_ID_Q2_BLANK_ACC_WIDTH (1U) 915 #define DBG_DBG_QMAN_ID_Q2_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_QMAN_ID_Q2_BLANK_ACC_SHIFT)) & DBG_DBG_QMAN_ID_Q2_BLANK_ACC_MASK) 916 917 #define DBG_DBG_QMAN_ID_Q3_BLANK_ACC_MASK (0x8U) 918 #define DBG_DBG_QMAN_ID_Q3_BLANK_ACC_SHIFT (3U) 919 #define DBG_DBG_QMAN_ID_Q3_BLANK_ACC_WIDTH (1U) 920 #define DBG_DBG_QMAN_ID_Q3_BLANK_ACC(x) (((uint32_t)(((uint32_t)(x)) << DBG_DBG_QMAN_ID_Q3_BLANK_ACC_SHIFT)) & DBG_DBG_QMAN_ID_Q3_BLANK_ACC_MASK) 921 /*! @} */ 922 923 /*! @name XCI_COR - MSS Acknowledge Control Register */ 924 /*! @{ */ 925 926 #define DBG_XCI_COR_INT_COUNT_MASK (0xFU) 927 #define DBG_XCI_COR_INT_COUNT_SHIFT (0U) 928 #define DBG_XCI_COR_INT_COUNT_WIDTH (4U) 929 #define DBG_XCI_COR_INT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DBG_XCI_COR_INT_COUNT_SHIFT)) & DBG_XCI_COR_INT_COUNT_MASK) 930 /*! @} */ 931 932 /*! 933 * @} 934 */ /* end of group DBG_Register_Masks */ 935 936 /*! 937 * @} 938 */ /* end of group DBG_Peripheral_Access_Layer */ 939 940 #endif /* #if !defined(S32Z2_DBG_H_) */ 941
