Home
last modified time | relevance | path

Searched refs:DBGMAILBOX_CSW_DBG_OR_ERR_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h7001 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7005 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h6956 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6960 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h6956 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6960 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h7001 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7005 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h7001 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7005 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h6956 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6960 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h6441 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6445 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h7383 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7387 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h7383 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7387 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h6440 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6444 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5512/
DLPC5512.h7431 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7435 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h6823 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6827 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h6822 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6826 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5514/
DLPC5514.h7432 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7436 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h7815 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7819 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h7814 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7818 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5516/
DLPC5516.h7433 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
7437 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h6823 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6827 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
DLPC55S66_cm33_core0.h6823 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6827 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h6822 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6826 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
DLPC55S69_cm33_core0.h6822 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
6826 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h23736 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
23742 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h23736 #define DBGMAILBOX_CSW_DBG_OR_ERR_MASK (0x4U) macro
23742 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_DBG_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_DBG_OR_ERR_MASK)