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Searched refs:DBGMAILBOX_CSW_AHB_OR_ERR_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502/
DLPC5502.h7007 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7011 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5502CPXXXX/
DLPC5502CPXXXX.h6962 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6966 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504CPXXXX/
DLPC5504CPXXXX.h6962 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6966 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5504/
DLPC5504.h7007 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7011 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506/
DLPC5506.h7007 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7011 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5506CPXXXX/
DLPC5506CPXXXX.h6962 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6966 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5526/
DLPC5526.h6447 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6451 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S06/
DLPC55S06.h7389 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7393 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S04/
DLPC55S04.h7389 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7393 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5528/
DLPC5528.h6446 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6450 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5512/
DLPC5512.h7437 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7441 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S26/
DLPC55S26.h6829 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6833 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S28/
DLPC55S28.h6828 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6832 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5514/
DLPC5514.h7438 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7442 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S16/
DLPC55S16.h7821 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7825 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S14/
DLPC55S14.h7820 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7824 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5516/
DLPC5516.h7439 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
7443 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S66/
DLPC55S66_cm33_core1.h6829 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6833 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
DLPC55S66_cm33_core0.h6829 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6833 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S69/
DLPC55S69_cm33_core1.h6828 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6832 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
DLPC55S69_cm33_core0.h6828 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
6832 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
DRW610.h23744 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
23750 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
DRW612.h23744 #define DBGMAILBOX_CSW_AHB_OR_ERR_MASK (0x8U) macro
23750 …(((uint32_t)(((uint32_t)(x)) << DBGMAILBOX_CSW_AHB_OR_ERR_SHIFT)) & DBGMAILBOX_CSW_AHB_OR_ERR_MASK)