| /hal_nxp-latest/mcux/mcux-sdk/drivers/ltc/ |
| D | fsl_ltc.c | 232 base->CW = (uint32_t)kLTC_ClearDataSize; in ltc_wait()
249 base->CW = (uint32_t)kLTC_ClearAll; in ltc_clear_all()
507 base->CW = (uint32_t)kLTC_ClearAll; in ltc_symmetric_alg_state()
1005 base->CW = (uint32_t)kLTC_ClearDataSize; in ltc_aes_received_mac_compare()
3133 base->CW = (uint32_t)kLTC_ClearAll; in ltc_hash_engine_init()
3245 base->CW = (uint32_t)kLTC_ClearKey; /* clear Key and Key Size registers */ in ltc_hash_restore_context()
3259 base->CW = (uint32_t)kLTC_ClearDataSize | (uint32_t)kLTC_ClearMode; in ltc_hash_prepare_context_switch()
3672 base->CW = (uint32_t)kLTC_ClearDataSize; in LTC_HASH_Update()
3714 base->CW = (uint32_t)kLTC_ClearDataSize; in LTC_HASH_Finish()
4001 base->CW = clearMask; in ltc_pkha_init_data()
[all …]
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| /hal_nxp-latest/mcux/mcux-sdk/drivers/cau3/ |
| D | fsl_cau3.c | 2285 base->CW = (uint32_t)kCAU3_ClearDataSize; in cau3_wait()
2302 base->CW = (uint32_t)kCAU3_ClearAll; in cau3_clear_all()
2538 base->CW = clearMask; in cau3_pkha_init_data()
3829 base->CW = clearMask; in CAU3_PKHA_ECC_PointAdd()
3917 base->CW = clearMask; in CAU3_PKHA_ECC_PointDouble()
4009 base->CW = clearMask; in CAU3_PKHA_ECC_PointMul()
4108 base->CW = clearMask; in CAU3_PKHA_ECM_PointMul()
4202 base->CW = clearMask; in CAU3_PKHA_ECT_PointMul()
4293 base->CW = clearMask; in CAU3_PKHA_ECT_PointAdd()
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| /hal_nxp-latest/mcux/middleware/wifi_nxp/ |
| D | README.txt | 40 * CW continuous wave\n
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/ |
| D | MKW30Z4.h | 3943 __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ member
3982 #define LTC_CW_REG(base) ((base)->CW)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/ |
| D | MKW20Z4.h | 3943 __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ member
3982 #define LTC_CW_REG(base) ((base)->CW)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/ |
| D | MKW40Z4.h | 3943 __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ member
3982 #define LTC_CW_REG(base) ((base)->CW)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW31Z4/ |
| D | MKW31Z4.h | 4047 __IO uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/K32L3A60/ |
| D | K32L3A60_cm4.h | 1639 __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */ member
|
| D | K32L3A60_cm0plus.h | 1284 __O uint32_t CW; /**< Clear Written Register, offset: 0x440 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW21Z4/ |
| D | MKW21Z4.h | 3976 __IO uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/ |
| D | MKW41Z4.h | 4047 __IO uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MK82F25615/ |
| D | MK82F25615.h | 16326 __O uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 16455 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 16456 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716A/ |
| D | MCXW716A.h | 22569 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW716C/ |
| D | MCXW716C.h | 24738 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| /hal_nxp-latest/mcux/mcux-sdk/devices/MCXW727C/ |
| D | MCXW727C_cm33_core0.h | 25642 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
| D | MCXW727C_cm33_core1.h | 33943 __O uint32_t CW; /**< Clear Written Register, offset: 0x40 */ member
|
