1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CTU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CTU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CTU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CTU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CTU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CTU_Peripheral_Access_Layer CTU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CTU - Size of Registers Arrays */ 72 #define CTU_TCR_COUNT 8u 73 #define CTU_CLR_COUNT 24u 74 #define CTU_FR_COUNT 4u 75 #define CTU_FL_COUNT 4u 76 77 /** CTU - Register Layout Typedef */ 78 typedef struct { 79 __IO uint32_t TGSISR; /**< Trigger Generator Subunit Input Selection Register, offset: 0x0 */ 80 __IO uint16_t TGSCR; /**< Trigger Generator Subunit Control Register, offset: 0x4 */ 81 __IO uint16_t TCR[CTU_TCR_COUNT]; /**< Trigger Compare Register, array offset: 0x6, array step: 0x2 */ 82 __IO uint16_t TGSCCR; /**< TGS Counter Compare Register, offset: 0x16 */ 83 __IO uint16_t TGSCRR; /**< TGS Counter Reload Register, offset: 0x18 */ 84 uint8_t RESERVED_0[2]; 85 __IO uint32_t CLCR1; /**< Commands List Control Register 1, offset: 0x1C */ 86 __IO uint32_t CLCR2; /**< Commands List Control Register 2, offset: 0x20 */ 87 __IO uint32_t THCR1; /**< Trigger Handler Control Register 1, offset: 0x24 */ 88 __IO uint32_t THCR2; /**< Trigger Handler Control Register 2, offset: 0x28 */ 89 union { /* offset: 0x2C */ 90 __IO uint16_t A[CTU_CLR_COUNT]; /**< Commands List Register A for ADC single-conversion mode commands, array offset: 0x2C, array step: 0x2 */ 91 __IO uint16_t B[CTU_CLR_COUNT]; /**< Command List Register B for ADC dual-conversion mode commands, array offset: 0x2C, array step: 0x2 */ 92 } CLR; 93 uint8_t RESERVED_1[16]; 94 __IO uint16_t FDCR; /**< FIFO DMA Control Register, offset: 0x6C */ 95 uint8_t RESERVED_2[2]; 96 __IO uint32_t FCR; /**< FIFO Control Register, offset: 0x70 */ 97 __IO uint32_t FTH; /**< FIFO Threshold Register, offset: 0x74 */ 98 uint8_t RESERVED_3[4]; 99 __IO uint32_t FST; /**< FIFO Status Register, offset: 0x7C */ 100 __I uint32_t FR[CTU_FR_COUNT]; /**< FIFO Right Aligned Data Register, array offset: 0x80, array step: 0x4 */ 101 uint8_t RESERVED_4[16]; 102 __I uint32_t FL[CTU_FL_COUNT]; /**< FIFO Signed Left Aligned Data Register, array offset: 0xA0, array step: 0x4 */ 103 uint8_t RESERVED_5[16]; 104 __IO uint16_t EFR; /**< Error Flag Register, offset: 0xC0 */ 105 __IO uint16_t IFR; /**< Interrupt Flag Register, offset: 0xC2 */ 106 __IO uint16_t IR; /**< Interrupt/DMA Register, offset: 0xC4 */ 107 __IO uint16_t COTR; /**< Control ON Time Register, offset: 0xC6 */ 108 __IO uint16_t CR; /**< Control Register, offset: 0xC8 */ 109 __IO uint16_t DFR; /**< Digital Filter Register, offset: 0xCA */ 110 __IO uint16_t EXPAR; /**< Expected Value A Register, offset: 0xCC */ 111 __IO uint16_t EXPBR; /**< Expected Value B Register, offset: 0xCE */ 112 __IO uint16_t CNTRNGR; /**< Counter Range Register, offset: 0xD0 */ 113 uint8_t RESERVED_6[2]; 114 __IO uint32_t LISTCSR; /**< List Control/Status Register, offset: 0xD4 */ 115 } CTU_Type, *CTU_MemMapPtr; 116 117 /** Number of instances of the CTU module. */ 118 #define CTU_INSTANCE_COUNT (1u) 119 120 /* CTU - Peripheral instance base addresses */ 121 /** Peripheral CTU base address */ 122 #define IP_CTU_BASE (0x40390000u) 123 /** Peripheral CTU base pointer */ 124 #define IP_CTU ((CTU_Type *)IP_CTU_BASE) 125 /** Array initializer of CTU peripheral base addresses */ 126 #define IP_CTU_BASE_ADDRS { IP_CTU_BASE } 127 /** Array initializer of CTU peripheral base pointers */ 128 #define IP_CTU_BASE_PTRS { IP_CTU } 129 130 /* ---------------------------------------------------------------------------- 131 -- CTU Register Masks 132 ---------------------------------------------------------------------------- */ 133 134 /*! 135 * @addtogroup CTU_Register_Masks CTU Register Masks 136 * @{ 137 */ 138 139 /*! @name TGSISR - Trigger Generator Subunit Input Selection Register */ 140 /*! @{ */ 141 142 #define CTU_TGSISR_I1_RE_MASK (0x4U) 143 #define CTU_TGSISR_I1_RE_SHIFT (2U) 144 #define CTU_TGSISR_I1_RE_WIDTH (1U) 145 #define CTU_TGSISR_I1_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I1_RE_SHIFT)) & CTU_TGSISR_I1_RE_MASK) 146 147 #define CTU_TGSISR_I1_FE_MASK (0x8U) 148 #define CTU_TGSISR_I1_FE_SHIFT (3U) 149 #define CTU_TGSISR_I1_FE_WIDTH (1U) 150 #define CTU_TGSISR_I1_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I1_FE_SHIFT)) & CTU_TGSISR_I1_FE_MASK) 151 152 #define CTU_TGSISR_I2_RE_MASK (0x10U) 153 #define CTU_TGSISR_I2_RE_SHIFT (4U) 154 #define CTU_TGSISR_I2_RE_WIDTH (1U) 155 #define CTU_TGSISR_I2_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I2_RE_SHIFT)) & CTU_TGSISR_I2_RE_MASK) 156 157 #define CTU_TGSISR_I2_FE_MASK (0x20U) 158 #define CTU_TGSISR_I2_FE_SHIFT (5U) 159 #define CTU_TGSISR_I2_FE_WIDTH (1U) 160 #define CTU_TGSISR_I2_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I2_FE_SHIFT)) & CTU_TGSISR_I2_FE_MASK) 161 162 #define CTU_TGSISR_I3_RE_MASK (0x40U) 163 #define CTU_TGSISR_I3_RE_SHIFT (6U) 164 #define CTU_TGSISR_I3_RE_WIDTH (1U) 165 #define CTU_TGSISR_I3_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I3_RE_SHIFT)) & CTU_TGSISR_I3_RE_MASK) 166 167 #define CTU_TGSISR_I3_FE_MASK (0x80U) 168 #define CTU_TGSISR_I3_FE_SHIFT (7U) 169 #define CTU_TGSISR_I3_FE_WIDTH (1U) 170 #define CTU_TGSISR_I3_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I3_FE_SHIFT)) & CTU_TGSISR_I3_FE_MASK) 171 172 #define CTU_TGSISR_I4_RE_MASK (0x100U) 173 #define CTU_TGSISR_I4_RE_SHIFT (8U) 174 #define CTU_TGSISR_I4_RE_WIDTH (1U) 175 #define CTU_TGSISR_I4_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I4_RE_SHIFT)) & CTU_TGSISR_I4_RE_MASK) 176 177 #define CTU_TGSISR_I4_FE_MASK (0x200U) 178 #define CTU_TGSISR_I4_FE_SHIFT (9U) 179 #define CTU_TGSISR_I4_FE_WIDTH (1U) 180 #define CTU_TGSISR_I4_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I4_FE_SHIFT)) & CTU_TGSISR_I4_FE_MASK) 181 182 #define CTU_TGSISR_I5_RE_MASK (0x400U) 183 #define CTU_TGSISR_I5_RE_SHIFT (10U) 184 #define CTU_TGSISR_I5_RE_WIDTH (1U) 185 #define CTU_TGSISR_I5_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I5_RE_SHIFT)) & CTU_TGSISR_I5_RE_MASK) 186 187 #define CTU_TGSISR_I5_FE_MASK (0x800U) 188 #define CTU_TGSISR_I5_FE_SHIFT (11U) 189 #define CTU_TGSISR_I5_FE_WIDTH (1U) 190 #define CTU_TGSISR_I5_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I5_FE_SHIFT)) & CTU_TGSISR_I5_FE_MASK) 191 192 #define CTU_TGSISR_I6_RE_MASK (0x1000U) 193 #define CTU_TGSISR_I6_RE_SHIFT (12U) 194 #define CTU_TGSISR_I6_RE_WIDTH (1U) 195 #define CTU_TGSISR_I6_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I6_RE_SHIFT)) & CTU_TGSISR_I6_RE_MASK) 196 197 #define CTU_TGSISR_I6_FE_MASK (0x2000U) 198 #define CTU_TGSISR_I6_FE_SHIFT (13U) 199 #define CTU_TGSISR_I6_FE_WIDTH (1U) 200 #define CTU_TGSISR_I6_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I6_FE_SHIFT)) & CTU_TGSISR_I6_FE_MASK) 201 202 #define CTU_TGSISR_I7_RE_MASK (0x4000U) 203 #define CTU_TGSISR_I7_RE_SHIFT (14U) 204 #define CTU_TGSISR_I7_RE_WIDTH (1U) 205 #define CTU_TGSISR_I7_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I7_RE_SHIFT)) & CTU_TGSISR_I7_RE_MASK) 206 207 #define CTU_TGSISR_I7_FE_MASK (0x8000U) 208 #define CTU_TGSISR_I7_FE_SHIFT (15U) 209 #define CTU_TGSISR_I7_FE_WIDTH (1U) 210 #define CTU_TGSISR_I7_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I7_FE_SHIFT)) & CTU_TGSISR_I7_FE_MASK) 211 212 #define CTU_TGSISR_I9_RE_MASK (0x40000U) 213 #define CTU_TGSISR_I9_RE_SHIFT (18U) 214 #define CTU_TGSISR_I9_RE_WIDTH (1U) 215 #define CTU_TGSISR_I9_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I9_RE_SHIFT)) & CTU_TGSISR_I9_RE_MASK) 216 217 #define CTU_TGSISR_I9_FE_MASK (0x80000U) 218 #define CTU_TGSISR_I9_FE_SHIFT (19U) 219 #define CTU_TGSISR_I9_FE_WIDTH (1U) 220 #define CTU_TGSISR_I9_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I9_FE_SHIFT)) & CTU_TGSISR_I9_FE_MASK) 221 222 #define CTU_TGSISR_I10_RE_MASK (0x100000U) 223 #define CTU_TGSISR_I10_RE_SHIFT (20U) 224 #define CTU_TGSISR_I10_RE_WIDTH (1U) 225 #define CTU_TGSISR_I10_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I10_RE_SHIFT)) & CTU_TGSISR_I10_RE_MASK) 226 227 #define CTU_TGSISR_I10_FE_MASK (0x200000U) 228 #define CTU_TGSISR_I10_FE_SHIFT (21U) 229 #define CTU_TGSISR_I10_FE_WIDTH (1U) 230 #define CTU_TGSISR_I10_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I10_FE_SHIFT)) & CTU_TGSISR_I10_FE_MASK) 231 232 #define CTU_TGSISR_I11_RE_MASK (0x400000U) 233 #define CTU_TGSISR_I11_RE_SHIFT (22U) 234 #define CTU_TGSISR_I11_RE_WIDTH (1U) 235 #define CTU_TGSISR_I11_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I11_RE_SHIFT)) & CTU_TGSISR_I11_RE_MASK) 236 237 #define CTU_TGSISR_I11_FE_MASK (0x800000U) 238 #define CTU_TGSISR_I11_FE_SHIFT (23U) 239 #define CTU_TGSISR_I11_FE_WIDTH (1U) 240 #define CTU_TGSISR_I11_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I11_FE_SHIFT)) & CTU_TGSISR_I11_FE_MASK) 241 242 #define CTU_TGSISR_I12_RE_MASK (0x1000000U) 243 #define CTU_TGSISR_I12_RE_SHIFT (24U) 244 #define CTU_TGSISR_I12_RE_WIDTH (1U) 245 #define CTU_TGSISR_I12_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I12_RE_SHIFT)) & CTU_TGSISR_I12_RE_MASK) 246 247 #define CTU_TGSISR_I12_FE_MASK (0x2000000U) 248 #define CTU_TGSISR_I12_FE_SHIFT (25U) 249 #define CTU_TGSISR_I12_FE_WIDTH (1U) 250 #define CTU_TGSISR_I12_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I12_FE_SHIFT)) & CTU_TGSISR_I12_FE_MASK) 251 252 #define CTU_TGSISR_I15_RE_MASK (0x40000000U) 253 #define CTU_TGSISR_I15_RE_SHIFT (30U) 254 #define CTU_TGSISR_I15_RE_WIDTH (1U) 255 #define CTU_TGSISR_I15_RE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I15_RE_SHIFT)) & CTU_TGSISR_I15_RE_MASK) 256 257 #define CTU_TGSISR_I15_FE_MASK (0x80000000U) 258 #define CTU_TGSISR_I15_FE_SHIFT (31U) 259 #define CTU_TGSISR_I15_FE_WIDTH (1U) 260 #define CTU_TGSISR_I15_FE(x) (((uint32_t)(((uint32_t)(x)) << CTU_TGSISR_I15_FE_SHIFT)) & CTU_TGSISR_I15_FE_MASK) 261 /*! @} */ 262 263 /*! @name TGSCR - Trigger Generator Subunit Control Register */ 264 /*! @{ */ 265 266 #define CTU_TGSCR_TGS_M_MASK (0x1U) 267 #define CTU_TGSCR_TGS_M_SHIFT (0U) 268 #define CTU_TGSCR_TGS_M_WIDTH (1U) 269 #define CTU_TGSCR_TGS_M(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCR_TGS_M_SHIFT)) & CTU_TGSCR_TGS_M_MASK) 270 271 #define CTU_TGSCR_MRS_SM_MASK (0x3EU) 272 #define CTU_TGSCR_MRS_SM_SHIFT (1U) 273 #define CTU_TGSCR_MRS_SM_WIDTH (5U) 274 #define CTU_TGSCR_MRS_SM(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCR_MRS_SM_SHIFT)) & CTU_TGSCR_MRS_SM_MASK) 275 276 #define CTU_TGSCR_PRES_MASK (0xC0U) 277 #define CTU_TGSCR_PRES_SHIFT (6U) 278 #define CTU_TGSCR_PRES_WIDTH (2U) 279 #define CTU_TGSCR_PRES(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCR_PRES_SHIFT)) & CTU_TGSCR_PRES_MASK) 280 281 #define CTU_TGSCR_ET_TM_MASK (0x100U) 282 #define CTU_TGSCR_ET_TM_SHIFT (8U) 283 #define CTU_TGSCR_ET_TM_WIDTH (1U) 284 #define CTU_TGSCR_ET_TM(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCR_ET_TM_SHIFT)) & CTU_TGSCR_ET_TM_MASK) 285 /*! @} */ 286 287 /*! @name TCR - Trigger Compare Register */ 288 /*! @{ */ 289 290 #define CTU_TCR_TCRV_MASK (0xFFFFU) 291 #define CTU_TCR_TCRV_SHIFT (0U) 292 #define CTU_TCR_TCRV_WIDTH (16U) 293 #define CTU_TCR_TCRV(x) (((uint16_t)(((uint16_t)(x)) << CTU_TCR_TCRV_SHIFT)) & CTU_TCR_TCRV_MASK) 294 /*! @} */ 295 296 /*! @name TGSCCR - TGS Counter Compare Register */ 297 /*! @{ */ 298 299 #define CTU_TGSCCR_TGSCCV_MASK (0xFFFFU) 300 #define CTU_TGSCCR_TGSCCV_SHIFT (0U) 301 #define CTU_TGSCCR_TGSCCV_WIDTH (16U) 302 #define CTU_TGSCCR_TGSCCV(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCCR_TGSCCV_SHIFT)) & CTU_TGSCCR_TGSCCV_MASK) 303 /*! @} */ 304 305 /*! @name TGSCRR - TGS Counter Reload Register */ 306 /*! @{ */ 307 308 #define CTU_TGSCRR_TGSCRV_MASK (0xFFFFU) 309 #define CTU_TGSCRR_TGSCRV_SHIFT (0U) 310 #define CTU_TGSCRR_TGSCRV_WIDTH (16U) 311 #define CTU_TGSCRR_TGSCRV(x) (((uint16_t)(((uint16_t)(x)) << CTU_TGSCRR_TGSCRV_SHIFT)) & CTU_TGSCRR_TGSCRV_MASK) 312 /*! @} */ 313 314 /*! @name CLCR1 - Commands List Control Register 1 */ 315 /*! @{ */ 316 317 #define CTU_CLCR1_T0_INDEX_MASK (0x1FU) 318 #define CTU_CLCR1_T0_INDEX_SHIFT (0U) 319 #define CTU_CLCR1_T0_INDEX_WIDTH (5U) 320 #define CTU_CLCR1_T0_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR1_T0_INDEX_SHIFT)) & CTU_CLCR1_T0_INDEX_MASK) 321 322 #define CTU_CLCR1_T1_INDEX_MASK (0x1F00U) 323 #define CTU_CLCR1_T1_INDEX_SHIFT (8U) 324 #define CTU_CLCR1_T1_INDEX_WIDTH (5U) 325 #define CTU_CLCR1_T1_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR1_T1_INDEX_SHIFT)) & CTU_CLCR1_T1_INDEX_MASK) 326 327 #define CTU_CLCR1_T2_INDEX_MASK (0x1F0000U) 328 #define CTU_CLCR1_T2_INDEX_SHIFT (16U) 329 #define CTU_CLCR1_T2_INDEX_WIDTH (5U) 330 #define CTU_CLCR1_T2_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR1_T2_INDEX_SHIFT)) & CTU_CLCR1_T2_INDEX_MASK) 331 332 #define CTU_CLCR1_T3_INDEX_MASK (0x1F000000U) 333 #define CTU_CLCR1_T3_INDEX_SHIFT (24U) 334 #define CTU_CLCR1_T3_INDEX_WIDTH (5U) 335 #define CTU_CLCR1_T3_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR1_T3_INDEX_SHIFT)) & CTU_CLCR1_T3_INDEX_MASK) 336 /*! @} */ 337 338 /*! @name CLCR2 - Commands List Control Register 2 */ 339 /*! @{ */ 340 341 #define CTU_CLCR2_T4_INDEX_MASK (0x1FU) 342 #define CTU_CLCR2_T4_INDEX_SHIFT (0U) 343 #define CTU_CLCR2_T4_INDEX_WIDTH (5U) 344 #define CTU_CLCR2_T4_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR2_T4_INDEX_SHIFT)) & CTU_CLCR2_T4_INDEX_MASK) 345 346 #define CTU_CLCR2_T5_INDEX_MASK (0x1F00U) 347 #define CTU_CLCR2_T5_INDEX_SHIFT (8U) 348 #define CTU_CLCR2_T5_INDEX_WIDTH (5U) 349 #define CTU_CLCR2_T5_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR2_T5_INDEX_SHIFT)) & CTU_CLCR2_T5_INDEX_MASK) 350 351 #define CTU_CLCR2_T6_INDEX_MASK (0x1F0000U) 352 #define CTU_CLCR2_T6_INDEX_SHIFT (16U) 353 #define CTU_CLCR2_T6_INDEX_WIDTH (5U) 354 #define CTU_CLCR2_T6_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR2_T6_INDEX_SHIFT)) & CTU_CLCR2_T6_INDEX_MASK) 355 356 #define CTU_CLCR2_T7_INDEX_MASK (0x1F000000U) 357 #define CTU_CLCR2_T7_INDEX_SHIFT (24U) 358 #define CTU_CLCR2_T7_INDEX_WIDTH (5U) 359 #define CTU_CLCR2_T7_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CTU_CLCR2_T7_INDEX_SHIFT)) & CTU_CLCR2_T7_INDEX_MASK) 360 /*! @} */ 361 362 /*! @name THCR1 - Trigger Handler Control Register 1 */ 363 /*! @{ */ 364 365 #define CTU_THCR1_T0_ADCE_MASK (0x1U) 366 #define CTU_THCR1_T0_ADCE_SHIFT (0U) 367 #define CTU_THCR1_T0_ADCE_WIDTH (1U) 368 #define CTU_THCR1_T0_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T0_ADCE_SHIFT)) & CTU_THCR1_T0_ADCE_MASK) 369 370 #define CTU_THCR1_T0_E_MASK (0x40U) 371 #define CTU_THCR1_T0_E_SHIFT (6U) 372 #define CTU_THCR1_T0_E_WIDTH (1U) 373 #define CTU_THCR1_T0_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T0_E_SHIFT)) & CTU_THCR1_T0_E_MASK) 374 375 #define CTU_THCR1_T1_ADCE_MASK (0x100U) 376 #define CTU_THCR1_T1_ADCE_SHIFT (8U) 377 #define CTU_THCR1_T1_ADCE_WIDTH (1U) 378 #define CTU_THCR1_T1_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T1_ADCE_SHIFT)) & CTU_THCR1_T1_ADCE_MASK) 379 380 #define CTU_THCR1_T1_E_MASK (0x4000U) 381 #define CTU_THCR1_T1_E_SHIFT (14U) 382 #define CTU_THCR1_T1_E_WIDTH (1U) 383 #define CTU_THCR1_T1_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T1_E_SHIFT)) & CTU_THCR1_T1_E_MASK) 384 385 #define CTU_THCR1_T2_ADCE_MASK (0x10000U) 386 #define CTU_THCR1_T2_ADCE_SHIFT (16U) 387 #define CTU_THCR1_T2_ADCE_WIDTH (1U) 388 #define CTU_THCR1_T2_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T2_ADCE_SHIFT)) & CTU_THCR1_T2_ADCE_MASK) 389 390 #define CTU_THCR1_T2_E_MASK (0x400000U) 391 #define CTU_THCR1_T2_E_SHIFT (22U) 392 #define CTU_THCR1_T2_E_WIDTH (1U) 393 #define CTU_THCR1_T2_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T2_E_SHIFT)) & CTU_THCR1_T2_E_MASK) 394 395 #define CTU_THCR1_T3_ADCE_MASK (0x1000000U) 396 #define CTU_THCR1_T3_ADCE_SHIFT (24U) 397 #define CTU_THCR1_T3_ADCE_WIDTH (1U) 398 #define CTU_THCR1_T3_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T3_ADCE_SHIFT)) & CTU_THCR1_T3_ADCE_MASK) 399 400 #define CTU_THCR1_T3_E_MASK (0x40000000U) 401 #define CTU_THCR1_T3_E_SHIFT (30U) 402 #define CTU_THCR1_T3_E_WIDTH (1U) 403 #define CTU_THCR1_T3_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR1_T3_E_SHIFT)) & CTU_THCR1_T3_E_MASK) 404 /*! @} */ 405 406 /*! @name THCR2 - Trigger Handler Control Register 2 */ 407 /*! @{ */ 408 409 #define CTU_THCR2_T4_ADCE_MASK (0x1U) 410 #define CTU_THCR2_T4_ADCE_SHIFT (0U) 411 #define CTU_THCR2_T4_ADCE_WIDTH (1U) 412 #define CTU_THCR2_T4_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T4_ADCE_SHIFT)) & CTU_THCR2_T4_ADCE_MASK) 413 414 #define CTU_THCR2_T4_E_MASK (0x40U) 415 #define CTU_THCR2_T4_E_SHIFT (6U) 416 #define CTU_THCR2_T4_E_WIDTH (1U) 417 #define CTU_THCR2_T4_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T4_E_SHIFT)) & CTU_THCR2_T4_E_MASK) 418 419 #define CTU_THCR2_T5_ADCE_MASK (0x100U) 420 #define CTU_THCR2_T5_ADCE_SHIFT (8U) 421 #define CTU_THCR2_T5_ADCE_WIDTH (1U) 422 #define CTU_THCR2_T5_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T5_ADCE_SHIFT)) & CTU_THCR2_T5_ADCE_MASK) 423 424 #define CTU_THCR2_T5_E_MASK (0x4000U) 425 #define CTU_THCR2_T5_E_SHIFT (14U) 426 #define CTU_THCR2_T5_E_WIDTH (1U) 427 #define CTU_THCR2_T5_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T5_E_SHIFT)) & CTU_THCR2_T5_E_MASK) 428 429 #define CTU_THCR2_T6_ADCE_MASK (0x10000U) 430 #define CTU_THCR2_T6_ADCE_SHIFT (16U) 431 #define CTU_THCR2_T6_ADCE_WIDTH (1U) 432 #define CTU_THCR2_T6_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T6_ADCE_SHIFT)) & CTU_THCR2_T6_ADCE_MASK) 433 434 #define CTU_THCR2_T6_E_MASK (0x400000U) 435 #define CTU_THCR2_T6_E_SHIFT (22U) 436 #define CTU_THCR2_T6_E_WIDTH (1U) 437 #define CTU_THCR2_T6_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T6_E_SHIFT)) & CTU_THCR2_T6_E_MASK) 438 439 #define CTU_THCR2_T7_ADCE_MASK (0x1000000U) 440 #define CTU_THCR2_T7_ADCE_SHIFT (24U) 441 #define CTU_THCR2_T7_ADCE_WIDTH (1U) 442 #define CTU_THCR2_T7_ADCE(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T7_ADCE_SHIFT)) & CTU_THCR2_T7_ADCE_MASK) 443 444 #define CTU_THCR2_T7_E_MASK (0x40000000U) 445 #define CTU_THCR2_T7_E_SHIFT (30U) 446 #define CTU_THCR2_T7_E_WIDTH (1U) 447 #define CTU_THCR2_T7_E(x) (((uint32_t)(((uint32_t)(x)) << CTU_THCR2_T7_E_SHIFT)) & CTU_THCR2_T7_E_MASK) 448 /*! @} */ 449 450 /*! @name A - Commands List Register A for ADC single-conversion mode commands */ 451 /*! @{ */ 452 453 #define CTU_A_CH_MASK (0xFU) 454 #define CTU_A_CH_SHIFT (0U) 455 #define CTU_A_CH_WIDTH (4U) 456 #define CTU_A_CH(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_CH_SHIFT)) & CTU_A_CH_MASK) 457 458 #define CTU_A_SU_MASK (0x20U) 459 #define CTU_A_SU_SHIFT (5U) 460 #define CTU_A_SU_WIDTH (1U) 461 #define CTU_A_SU(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_SU_SHIFT)) & CTU_A_SU_MASK) 462 463 #define CTU_A_FIFO_MASK (0x1C00U) 464 #define CTU_A_FIFO_SHIFT (10U) 465 #define CTU_A_FIFO_WIDTH (3U) 466 #define CTU_A_FIFO(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_FIFO_SHIFT)) & CTU_A_FIFO_MASK) 467 468 #define CTU_A_CMS_MASK (0x2000U) 469 #define CTU_A_CMS_SHIFT (13U) 470 #define CTU_A_CMS_WIDTH (1U) 471 #define CTU_A_CMS(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_CMS_SHIFT)) & CTU_A_CMS_MASK) 472 473 #define CTU_A_LC_MASK (0x4000U) 474 #define CTU_A_LC_SHIFT (14U) 475 #define CTU_A_LC_WIDTH (1U) 476 #define CTU_A_LC(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_LC_SHIFT)) & CTU_A_LC_MASK) 477 478 #define CTU_A_CIR_MASK (0x8000U) 479 #define CTU_A_CIR_SHIFT (15U) 480 #define CTU_A_CIR_WIDTH (1U) 481 #define CTU_A_CIR(x) (((uint16_t)(((uint16_t)(x)) << CTU_A_CIR_SHIFT)) & CTU_A_CIR_MASK) 482 /*! @} */ 483 484 /*! @name B - Command List Register B for ADC dual-conversion mode commands */ 485 /*! @{ */ 486 487 #define CTU_B_CH_A_MASK (0xFU) 488 #define CTU_B_CH_A_SHIFT (0U) 489 #define CTU_B_CH_A_WIDTH (4U) 490 #define CTU_B_CH_A(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_CH_A_SHIFT)) & CTU_B_CH_A_MASK) 491 492 #define CTU_B_CH_B_MASK (0x1E0U) 493 #define CTU_B_CH_B_SHIFT (5U) 494 #define CTU_B_CH_B_WIDTH (4U) 495 #define CTU_B_CH_B(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_CH_B_SHIFT)) & CTU_B_CH_B_MASK) 496 497 #define CTU_B_FIFO_MASK (0x1C00U) 498 #define CTU_B_FIFO_SHIFT (10U) 499 #define CTU_B_FIFO_WIDTH (3U) 500 #define CTU_B_FIFO(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_FIFO_SHIFT)) & CTU_B_FIFO_MASK) 501 502 #define CTU_B_CMS_MASK (0x2000U) 503 #define CTU_B_CMS_SHIFT (13U) 504 #define CTU_B_CMS_WIDTH (1U) 505 #define CTU_B_CMS(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_CMS_SHIFT)) & CTU_B_CMS_MASK) 506 507 #define CTU_B_LC_MASK (0x4000U) 508 #define CTU_B_LC_SHIFT (14U) 509 #define CTU_B_LC_WIDTH (1U) 510 #define CTU_B_LC(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_LC_SHIFT)) & CTU_B_LC_MASK) 511 512 #define CTU_B_CIR_MASK (0x8000U) 513 #define CTU_B_CIR_SHIFT (15U) 514 #define CTU_B_CIR_WIDTH (1U) 515 #define CTU_B_CIR(x) (((uint16_t)(((uint16_t)(x)) << CTU_B_CIR_SHIFT)) & CTU_B_CIR_MASK) 516 /*! @} */ 517 518 /*! @name FDCR - FIFO DMA Control Register */ 519 /*! @{ */ 520 521 #define CTU_FDCR_DE0_MASK (0x1U) 522 #define CTU_FDCR_DE0_SHIFT (0U) 523 #define CTU_FDCR_DE0_WIDTH (1U) 524 #define CTU_FDCR_DE0(x) (((uint16_t)(((uint16_t)(x)) << CTU_FDCR_DE0_SHIFT)) & CTU_FDCR_DE0_MASK) 525 526 #define CTU_FDCR_DE1_MASK (0x2U) 527 #define CTU_FDCR_DE1_SHIFT (1U) 528 #define CTU_FDCR_DE1_WIDTH (1U) 529 #define CTU_FDCR_DE1(x) (((uint16_t)(((uint16_t)(x)) << CTU_FDCR_DE1_SHIFT)) & CTU_FDCR_DE1_MASK) 530 531 #define CTU_FDCR_DE2_MASK (0x4U) 532 #define CTU_FDCR_DE2_SHIFT (2U) 533 #define CTU_FDCR_DE2_WIDTH (1U) 534 #define CTU_FDCR_DE2(x) (((uint16_t)(((uint16_t)(x)) << CTU_FDCR_DE2_SHIFT)) & CTU_FDCR_DE2_MASK) 535 536 #define CTU_FDCR_DE3_MASK (0x8U) 537 #define CTU_FDCR_DE3_SHIFT (3U) 538 #define CTU_FDCR_DE3_WIDTH (1U) 539 #define CTU_FDCR_DE3(x) (((uint16_t)(((uint16_t)(x)) << CTU_FDCR_DE3_SHIFT)) & CTU_FDCR_DE3_MASK) 540 /*! @} */ 541 542 /*! @name FCR - FIFO Control Register */ 543 /*! @{ */ 544 545 #define CTU_FCR_FULL_EN0_MASK (0x1U) 546 #define CTU_FCR_FULL_EN0_SHIFT (0U) 547 #define CTU_FCR_FULL_EN0_WIDTH (1U) 548 #define CTU_FCR_FULL_EN0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_FULL_EN0_SHIFT)) & CTU_FCR_FULL_EN0_MASK) 549 550 #define CTU_FCR_EMPTY_EN0_MASK (0x2U) 551 #define CTU_FCR_EMPTY_EN0_SHIFT (1U) 552 #define CTU_FCR_EMPTY_EN0_WIDTH (1U) 553 #define CTU_FCR_EMPTY_EN0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_EMPTY_EN0_SHIFT)) & CTU_FCR_EMPTY_EN0_MASK) 554 555 #define CTU_FCR_OF_EN0_MASK (0x4U) 556 #define CTU_FCR_OF_EN0_SHIFT (2U) 557 #define CTU_FCR_OF_EN0_WIDTH (1U) 558 #define CTU_FCR_OF_EN0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OF_EN0_SHIFT)) & CTU_FCR_OF_EN0_MASK) 559 560 #define CTU_FCR_OR_EN0_MASK (0x8U) 561 #define CTU_FCR_OR_EN0_SHIFT (3U) 562 #define CTU_FCR_OR_EN0_WIDTH (1U) 563 #define CTU_FCR_OR_EN0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OR_EN0_SHIFT)) & CTU_FCR_OR_EN0_MASK) 564 565 #define CTU_FCR_FULL_EN1_MASK (0x10U) 566 #define CTU_FCR_FULL_EN1_SHIFT (4U) 567 #define CTU_FCR_FULL_EN1_WIDTH (1U) 568 #define CTU_FCR_FULL_EN1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_FULL_EN1_SHIFT)) & CTU_FCR_FULL_EN1_MASK) 569 570 #define CTU_FCR_EMPTY_EN1_MASK (0x20U) 571 #define CTU_FCR_EMPTY_EN1_SHIFT (5U) 572 #define CTU_FCR_EMPTY_EN1_WIDTH (1U) 573 #define CTU_FCR_EMPTY_EN1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_EMPTY_EN1_SHIFT)) & CTU_FCR_EMPTY_EN1_MASK) 574 575 #define CTU_FCR_OF_EN1_MASK (0x40U) 576 #define CTU_FCR_OF_EN1_SHIFT (6U) 577 #define CTU_FCR_OF_EN1_WIDTH (1U) 578 #define CTU_FCR_OF_EN1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OF_EN1_SHIFT)) & CTU_FCR_OF_EN1_MASK) 579 580 #define CTU_FCR_OR_EN1_MASK (0x80U) 581 #define CTU_FCR_OR_EN1_SHIFT (7U) 582 #define CTU_FCR_OR_EN1_WIDTH (1U) 583 #define CTU_FCR_OR_EN1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OR_EN1_SHIFT)) & CTU_FCR_OR_EN1_MASK) 584 585 #define CTU_FCR_FULL_EN2_MASK (0x100U) 586 #define CTU_FCR_FULL_EN2_SHIFT (8U) 587 #define CTU_FCR_FULL_EN2_WIDTH (1U) 588 #define CTU_FCR_FULL_EN2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_FULL_EN2_SHIFT)) & CTU_FCR_FULL_EN2_MASK) 589 590 #define CTU_FCR_EMPTY_EN2_MASK (0x200U) 591 #define CTU_FCR_EMPTY_EN2_SHIFT (9U) 592 #define CTU_FCR_EMPTY_EN2_WIDTH (1U) 593 #define CTU_FCR_EMPTY_EN2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_EMPTY_EN2_SHIFT)) & CTU_FCR_EMPTY_EN2_MASK) 594 595 #define CTU_FCR_OF_EN2_MASK (0x400U) 596 #define CTU_FCR_OF_EN2_SHIFT (10U) 597 #define CTU_FCR_OF_EN2_WIDTH (1U) 598 #define CTU_FCR_OF_EN2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OF_EN2_SHIFT)) & CTU_FCR_OF_EN2_MASK) 599 600 #define CTU_FCR_OR_EN2_MASK (0x800U) 601 #define CTU_FCR_OR_EN2_SHIFT (11U) 602 #define CTU_FCR_OR_EN2_WIDTH (1U) 603 #define CTU_FCR_OR_EN2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OR_EN2_SHIFT)) & CTU_FCR_OR_EN2_MASK) 604 605 #define CTU_FCR_FULL_EN3_MASK (0x1000U) 606 #define CTU_FCR_FULL_EN3_SHIFT (12U) 607 #define CTU_FCR_FULL_EN3_WIDTH (1U) 608 #define CTU_FCR_FULL_EN3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_FULL_EN3_SHIFT)) & CTU_FCR_FULL_EN3_MASK) 609 610 #define CTU_FCR_EMPTY_EN3_MASK (0x2000U) 611 #define CTU_FCR_EMPTY_EN3_SHIFT (13U) 612 #define CTU_FCR_EMPTY_EN3_WIDTH (1U) 613 #define CTU_FCR_EMPTY_EN3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_EMPTY_EN3_SHIFT)) & CTU_FCR_EMPTY_EN3_MASK) 614 615 #define CTU_FCR_OF_EN3_MASK (0x4000U) 616 #define CTU_FCR_OF_EN3_SHIFT (14U) 617 #define CTU_FCR_OF_EN3_WIDTH (1U) 618 #define CTU_FCR_OF_EN3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OF_EN3_SHIFT)) & CTU_FCR_OF_EN3_MASK) 619 620 #define CTU_FCR_OR_EN3_MASK (0x8000U) 621 #define CTU_FCR_OR_EN3_SHIFT (15U) 622 #define CTU_FCR_OR_EN3_WIDTH (1U) 623 #define CTU_FCR_OR_EN3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FCR_OR_EN3_SHIFT)) & CTU_FCR_OR_EN3_MASK) 624 /*! @} */ 625 626 /*! @name FTH - FIFO Threshold Register */ 627 /*! @{ */ 628 629 #define CTU_FTH_TH0_MASK (0xFFU) 630 #define CTU_FTH_TH0_SHIFT (0U) 631 #define CTU_FTH_TH0_WIDTH (8U) 632 #define CTU_FTH_TH0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FTH_TH0_SHIFT)) & CTU_FTH_TH0_MASK) 633 634 #define CTU_FTH_TH1_MASK (0xFF00U) 635 #define CTU_FTH_TH1_SHIFT (8U) 636 #define CTU_FTH_TH1_WIDTH (8U) 637 #define CTU_FTH_TH1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FTH_TH1_SHIFT)) & CTU_FTH_TH1_MASK) 638 639 #define CTU_FTH_TH2_MASK (0xFF0000U) 640 #define CTU_FTH_TH2_SHIFT (16U) 641 #define CTU_FTH_TH2_WIDTH (8U) 642 #define CTU_FTH_TH2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FTH_TH2_SHIFT)) & CTU_FTH_TH2_MASK) 643 644 #define CTU_FTH_TH3_MASK (0xFF000000U) 645 #define CTU_FTH_TH3_SHIFT (24U) 646 #define CTU_FTH_TH3_WIDTH (8U) 647 #define CTU_FTH_TH3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FTH_TH3_SHIFT)) & CTU_FTH_TH3_MASK) 648 /*! @} */ 649 650 /*! @name FST - FIFO Status Register */ 651 /*! @{ */ 652 653 #define CTU_FST_FULL0_MASK (0x1U) 654 #define CTU_FST_FULL0_SHIFT (0U) 655 #define CTU_FST_FULL0_WIDTH (1U) 656 #define CTU_FST_FULL0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_FULL0_SHIFT)) & CTU_FST_FULL0_MASK) 657 658 #define CTU_FST_EMP0_MASK (0x2U) 659 #define CTU_FST_EMP0_SHIFT (1U) 660 #define CTU_FST_EMP0_WIDTH (1U) 661 #define CTU_FST_EMP0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_EMP0_SHIFT)) & CTU_FST_EMP0_MASK) 662 663 #define CTU_FST_OF0_MASK (0x4U) 664 #define CTU_FST_OF0_SHIFT (2U) 665 #define CTU_FST_OF0_WIDTH (1U) 666 #define CTU_FST_OF0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OF0_SHIFT)) & CTU_FST_OF0_MASK) 667 668 #define CTU_FST_OR0_MASK (0x8U) 669 #define CTU_FST_OR0_SHIFT (3U) 670 #define CTU_FST_OR0_WIDTH (1U) 671 #define CTU_FST_OR0(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OR0_SHIFT)) & CTU_FST_OR0_MASK) 672 673 #define CTU_FST_FULL1_MASK (0x10U) 674 #define CTU_FST_FULL1_SHIFT (4U) 675 #define CTU_FST_FULL1_WIDTH (1U) 676 #define CTU_FST_FULL1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_FULL1_SHIFT)) & CTU_FST_FULL1_MASK) 677 678 #define CTU_FST_EMP1_MASK (0x20U) 679 #define CTU_FST_EMP1_SHIFT (5U) 680 #define CTU_FST_EMP1_WIDTH (1U) 681 #define CTU_FST_EMP1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_EMP1_SHIFT)) & CTU_FST_EMP1_MASK) 682 683 #define CTU_FST_OF1_MASK (0x40U) 684 #define CTU_FST_OF1_SHIFT (6U) 685 #define CTU_FST_OF1_WIDTH (1U) 686 #define CTU_FST_OF1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OF1_SHIFT)) & CTU_FST_OF1_MASK) 687 688 #define CTU_FST_OR1_MASK (0x80U) 689 #define CTU_FST_OR1_SHIFT (7U) 690 #define CTU_FST_OR1_WIDTH (1U) 691 #define CTU_FST_OR1(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OR1_SHIFT)) & CTU_FST_OR1_MASK) 692 693 #define CTU_FST_FULL2_MASK (0x100U) 694 #define CTU_FST_FULL2_SHIFT (8U) 695 #define CTU_FST_FULL2_WIDTH (1U) 696 #define CTU_FST_FULL2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_FULL2_SHIFT)) & CTU_FST_FULL2_MASK) 697 698 #define CTU_FST_EMP2_MASK (0x200U) 699 #define CTU_FST_EMP2_SHIFT (9U) 700 #define CTU_FST_EMP2_WIDTH (1U) 701 #define CTU_FST_EMP2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_EMP2_SHIFT)) & CTU_FST_EMP2_MASK) 702 703 #define CTU_FST_OF2_MASK (0x400U) 704 #define CTU_FST_OF2_SHIFT (10U) 705 #define CTU_FST_OF2_WIDTH (1U) 706 #define CTU_FST_OF2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OF2_SHIFT)) & CTU_FST_OF2_MASK) 707 708 #define CTU_FST_OR2_MASK (0x800U) 709 #define CTU_FST_OR2_SHIFT (11U) 710 #define CTU_FST_OR2_WIDTH (1U) 711 #define CTU_FST_OR2(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OR2_SHIFT)) & CTU_FST_OR2_MASK) 712 713 #define CTU_FST_FULL3_MASK (0x1000U) 714 #define CTU_FST_FULL3_SHIFT (12U) 715 #define CTU_FST_FULL3_WIDTH (1U) 716 #define CTU_FST_FULL3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_FULL3_SHIFT)) & CTU_FST_FULL3_MASK) 717 718 #define CTU_FST_EMP3_MASK (0x2000U) 719 #define CTU_FST_EMP3_SHIFT (13U) 720 #define CTU_FST_EMP3_WIDTH (1U) 721 #define CTU_FST_EMP3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_EMP3_SHIFT)) & CTU_FST_EMP3_MASK) 722 723 #define CTU_FST_OF3_MASK (0x4000U) 724 #define CTU_FST_OF3_SHIFT (14U) 725 #define CTU_FST_OF3_WIDTH (1U) 726 #define CTU_FST_OF3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OF3_SHIFT)) & CTU_FST_OF3_MASK) 727 728 #define CTU_FST_OR3_MASK (0x8000U) 729 #define CTU_FST_OR3_SHIFT (15U) 730 #define CTU_FST_OR3_WIDTH (1U) 731 #define CTU_FST_OR3(x) (((uint32_t)(((uint32_t)(x)) << CTU_FST_OR3_SHIFT)) & CTU_FST_OR3_MASK) 732 /*! @} */ 733 734 /*! @name FR - FIFO Right Aligned Data Register */ 735 /*! @{ */ 736 737 #define CTU_FR_DATA_MASK (0xFFFU) 738 #define CTU_FR_DATA_SHIFT (0U) 739 #define CTU_FR_DATA_WIDTH (12U) 740 #define CTU_FR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CTU_FR_DATA_SHIFT)) & CTU_FR_DATA_MASK) 741 742 #define CTU_FR_N_CH_MASK (0x70000U) 743 #define CTU_FR_N_CH_SHIFT (16U) 744 #define CTU_FR_N_CH_WIDTH (3U) 745 #define CTU_FR_N_CH(x) (((uint32_t)(((uint32_t)(x)) << CTU_FR_N_CH_SHIFT)) & CTU_FR_N_CH_MASK) 746 747 #define CTU_FR_ADC_MASK (0x80000U) 748 #define CTU_FR_ADC_SHIFT (19U) 749 #define CTU_FR_ADC_WIDTH (1U) 750 #define CTU_FR_ADC(x) (((uint32_t)(((uint32_t)(x)) << CTU_FR_ADC_SHIFT)) & CTU_FR_ADC_MASK) 751 /*! @} */ 752 753 /*! @name FL - FIFO Signed Left Aligned Data Register */ 754 /*! @{ */ 755 756 #define CTU_FL_LA_DATA_MASK (0x7FF8U) 757 #define CTU_FL_LA_DATA_SHIFT (3U) 758 #define CTU_FL_LA_DATA_WIDTH (12U) 759 #define CTU_FL_LA_DATA(x) (((uint32_t)(((uint32_t)(x)) << CTU_FL_LA_DATA_SHIFT)) & CTU_FL_LA_DATA_MASK) 760 761 #define CTU_FL_N_CH_MASK (0x70000U) 762 #define CTU_FL_N_CH_SHIFT (16U) 763 #define CTU_FL_N_CH_WIDTH (3U) 764 #define CTU_FL_N_CH(x) (((uint32_t)(((uint32_t)(x)) << CTU_FL_N_CH_SHIFT)) & CTU_FL_N_CH_MASK) 765 766 #define CTU_FL_ADC_MASK (0x80000U) 767 #define CTU_FL_ADC_SHIFT (19U) 768 #define CTU_FL_ADC_WIDTH (1U) 769 #define CTU_FL_ADC(x) (((uint32_t)(((uint32_t)(x)) << CTU_FL_ADC_SHIFT)) & CTU_FL_ADC_MASK) 770 /*! @} */ 771 772 /*! @name EFR - Error Flag Register */ 773 /*! @{ */ 774 775 #define CTU_EFR_MRS_RE_MASK (0x1U) 776 #define CTU_EFR_MRS_RE_SHIFT (0U) 777 #define CTU_EFR_MRS_RE_WIDTH (1U) 778 #define CTU_EFR_MRS_RE(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_MRS_RE_SHIFT)) & CTU_EFR_MRS_RE_MASK) 779 780 #define CTU_EFR_SM_TO_MASK (0x2U) 781 #define CTU_EFR_SM_TO_SHIFT (1U) 782 #define CTU_EFR_SM_TO_WIDTH (1U) 783 #define CTU_EFR_SM_TO(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_SM_TO_SHIFT)) & CTU_EFR_SM_TO_MASK) 784 785 #define CTU_EFR_ICE_MASK (0x4U) 786 #define CTU_EFR_ICE_SHIFT (2U) 787 #define CTU_EFR_ICE_WIDTH (1U) 788 #define CTU_EFR_ICE(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_ICE_SHIFT)) & CTU_EFR_ICE_MASK) 789 790 #define CTU_EFR_MRS_O_MASK (0x8U) 791 #define CTU_EFR_MRS_O_SHIFT (3U) 792 #define CTU_EFR_MRS_O_WIDTH (1U) 793 #define CTU_EFR_MRS_O(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_MRS_O_SHIFT)) & CTU_EFR_MRS_O_MASK) 794 795 #define CTU_EFR_TGS_OSM_MASK (0x10U) 796 #define CTU_EFR_TGS_OSM_SHIFT (4U) 797 #define CTU_EFR_TGS_OSM_WIDTH (1U) 798 #define CTU_EFR_TGS_OSM(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_TGS_OSM_SHIFT)) & CTU_EFR_TGS_OSM_MASK) 799 800 #define CTU_EFR_ADC_OE_MASK (0x20U) 801 #define CTU_EFR_ADC_OE_SHIFT (5U) 802 #define CTU_EFR_ADC_OE_WIDTH (1U) 803 #define CTU_EFR_ADC_OE(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_ADC_OE_SHIFT)) & CTU_EFR_ADC_OE_MASK) 804 805 #define CTU_EFR_ERRCMP_MASK (0x400U) 806 #define CTU_EFR_ERRCMP_SHIFT (10U) 807 #define CTU_EFR_ERRCMP_WIDTH (1U) 808 #define CTU_EFR_ERRCMP(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_ERRCMP_SHIFT)) & CTU_EFR_ERRCMP_MASK) 809 810 #define CTU_EFR_LIST_BE_MASK (0x2000U) 811 #define CTU_EFR_LIST_BE_SHIFT (13U) 812 #define CTU_EFR_LIST_BE_WIDTH (1U) 813 #define CTU_EFR_LIST_BE(x) (((uint16_t)(((uint16_t)(x)) << CTU_EFR_LIST_BE_SHIFT)) & CTU_EFR_LIST_BE_MASK) 814 /*! @} */ 815 816 /*! @name IFR - Interrupt Flag Register */ 817 /*! @{ */ 818 819 #define CTU_IFR_MRS_I_MASK (0x1U) 820 #define CTU_IFR_MRS_I_SHIFT (0U) 821 #define CTU_IFR_MRS_I_WIDTH (1U) 822 #define CTU_IFR_MRS_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_MRS_I_SHIFT)) & CTU_IFR_MRS_I_MASK) 823 824 #define CTU_IFR_T0_I_MASK (0x2U) 825 #define CTU_IFR_T0_I_SHIFT (1U) 826 #define CTU_IFR_T0_I_WIDTH (1U) 827 #define CTU_IFR_T0_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T0_I_SHIFT)) & CTU_IFR_T0_I_MASK) 828 829 #define CTU_IFR_T1_I_MASK (0x4U) 830 #define CTU_IFR_T1_I_SHIFT (2U) 831 #define CTU_IFR_T1_I_WIDTH (1U) 832 #define CTU_IFR_T1_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T1_I_SHIFT)) & CTU_IFR_T1_I_MASK) 833 834 #define CTU_IFR_T2_I_MASK (0x8U) 835 #define CTU_IFR_T2_I_SHIFT (3U) 836 #define CTU_IFR_T2_I_WIDTH (1U) 837 #define CTU_IFR_T2_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T2_I_SHIFT)) & CTU_IFR_T2_I_MASK) 838 839 #define CTU_IFR_T3_I_MASK (0x10U) 840 #define CTU_IFR_T3_I_SHIFT (4U) 841 #define CTU_IFR_T3_I_WIDTH (1U) 842 #define CTU_IFR_T3_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T3_I_SHIFT)) & CTU_IFR_T3_I_MASK) 843 844 #define CTU_IFR_T4_I_MASK (0x20U) 845 #define CTU_IFR_T4_I_SHIFT (5U) 846 #define CTU_IFR_T4_I_WIDTH (1U) 847 #define CTU_IFR_T4_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T4_I_SHIFT)) & CTU_IFR_T4_I_MASK) 848 849 #define CTU_IFR_T5_I_MASK (0x40U) 850 #define CTU_IFR_T5_I_SHIFT (6U) 851 #define CTU_IFR_T5_I_WIDTH (1U) 852 #define CTU_IFR_T5_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T5_I_SHIFT)) & CTU_IFR_T5_I_MASK) 853 854 #define CTU_IFR_T6_I_MASK (0x80U) 855 #define CTU_IFR_T6_I_SHIFT (7U) 856 #define CTU_IFR_T6_I_WIDTH (1U) 857 #define CTU_IFR_T6_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T6_I_SHIFT)) & CTU_IFR_T6_I_MASK) 858 859 #define CTU_IFR_T7_I_MASK (0x100U) 860 #define CTU_IFR_T7_I_SHIFT (8U) 861 #define CTU_IFR_T7_I_WIDTH (1U) 862 #define CTU_IFR_T7_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_T7_I_SHIFT)) & CTU_IFR_T7_I_MASK) 863 864 #define CTU_IFR_ADC_I_MASK (0x200U) 865 #define CTU_IFR_ADC_I_SHIFT (9U) 866 #define CTU_IFR_ADC_I_WIDTH (1U) 867 #define CTU_IFR_ADC_I(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_ADC_I_SHIFT)) & CTU_IFR_ADC_I_MASK) 868 869 #define CTU_IFR_SERR_A_MASK (0x400U) 870 #define CTU_IFR_SERR_A_SHIFT (10U) 871 #define CTU_IFR_SERR_A_WIDTH (1U) 872 #define CTU_IFR_SERR_A(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_SERR_A_SHIFT)) & CTU_IFR_SERR_A_MASK) 873 874 #define CTU_IFR_SERR_B_MASK (0x800U) 875 #define CTU_IFR_SERR_B_SHIFT (11U) 876 #define CTU_IFR_SERR_B_WIDTH (1U) 877 #define CTU_IFR_SERR_B(x) (((uint16_t)(((uint16_t)(x)) << CTU_IFR_SERR_B_SHIFT)) & CTU_IFR_SERR_B_MASK) 878 /*! @} */ 879 880 /*! @name IR - Interrupt/DMA Register */ 881 /*! @{ */ 882 883 #define CTU_IR_IEE_MASK (0x1U) 884 #define CTU_IR_IEE_SHIFT (0U) 885 #define CTU_IR_IEE_WIDTH (1U) 886 #define CTU_IR_IEE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_IEE_SHIFT)) & CTU_IR_IEE_MASK) 887 888 #define CTU_IR_MRS_IE_MASK (0x2U) 889 #define CTU_IR_MRS_IE_SHIFT (1U) 890 #define CTU_IR_MRS_IE_WIDTH (1U) 891 #define CTU_IR_MRS_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_MRS_IE_SHIFT)) & CTU_IR_MRS_IE_MASK) 892 893 #define CTU_IR_MRS_DMAE_MASK (0x4U) 894 #define CTU_IR_MRS_DMAE_SHIFT (2U) 895 #define CTU_IR_MRS_DMAE_WIDTH (1U) 896 #define CTU_IR_MRS_DMAE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_MRS_DMAE_SHIFT)) & CTU_IR_MRS_DMAE_MASK) 897 898 #define CTU_IR_DMA_DE_MASK (0x8U) 899 #define CTU_IR_DMA_DE_SHIFT (3U) 900 #define CTU_IR_DMA_DE_WIDTH (1U) 901 #define CTU_IR_DMA_DE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_DMA_DE_SHIFT)) & CTU_IR_DMA_DE_MASK) 902 903 #define CTU_IR_SAF_CNT_A_EN_MASK (0x10U) 904 #define CTU_IR_SAF_CNT_A_EN_SHIFT (4U) 905 #define CTU_IR_SAF_CNT_A_EN_WIDTH (1U) 906 #define CTU_IR_SAF_CNT_A_EN(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_SAF_CNT_A_EN_SHIFT)) & CTU_IR_SAF_CNT_A_EN_MASK) 907 908 #define CTU_IR_SAF_CNT_B_EN_MASK (0x20U) 909 #define CTU_IR_SAF_CNT_B_EN_SHIFT (5U) 910 #define CTU_IR_SAF_CNT_B_EN_WIDTH (1U) 911 #define CTU_IR_SAF_CNT_B_EN(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_SAF_CNT_B_EN_SHIFT)) & CTU_IR_SAF_CNT_B_EN_MASK) 912 913 #define CTU_IR_T0_IE_MASK (0x100U) 914 #define CTU_IR_T0_IE_SHIFT (8U) 915 #define CTU_IR_T0_IE_WIDTH (1U) 916 #define CTU_IR_T0_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T0_IE_SHIFT)) & CTU_IR_T0_IE_MASK) 917 918 #define CTU_IR_T1_IE_MASK (0x200U) 919 #define CTU_IR_T1_IE_SHIFT (9U) 920 #define CTU_IR_T1_IE_WIDTH (1U) 921 #define CTU_IR_T1_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T1_IE_SHIFT)) & CTU_IR_T1_IE_MASK) 922 923 #define CTU_IR_T2_IE_MASK (0x400U) 924 #define CTU_IR_T2_IE_SHIFT (10U) 925 #define CTU_IR_T2_IE_WIDTH (1U) 926 #define CTU_IR_T2_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T2_IE_SHIFT)) & CTU_IR_T2_IE_MASK) 927 928 #define CTU_IR_T3_IE_MASK (0x800U) 929 #define CTU_IR_T3_IE_SHIFT (11U) 930 #define CTU_IR_T3_IE_WIDTH (1U) 931 #define CTU_IR_T3_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T3_IE_SHIFT)) & CTU_IR_T3_IE_MASK) 932 933 #define CTU_IR_T4_IE_MASK (0x1000U) 934 #define CTU_IR_T4_IE_SHIFT (12U) 935 #define CTU_IR_T4_IE_WIDTH (1U) 936 #define CTU_IR_T4_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T4_IE_SHIFT)) & CTU_IR_T4_IE_MASK) 937 938 #define CTU_IR_T5_IE_MASK (0x2000U) 939 #define CTU_IR_T5_IE_SHIFT (13U) 940 #define CTU_IR_T5_IE_WIDTH (1U) 941 #define CTU_IR_T5_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T5_IE_SHIFT)) & CTU_IR_T5_IE_MASK) 942 943 #define CTU_IR_T6_IE_MASK (0x4000U) 944 #define CTU_IR_T6_IE_SHIFT (14U) 945 #define CTU_IR_T6_IE_WIDTH (1U) 946 #define CTU_IR_T6_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T6_IE_SHIFT)) & CTU_IR_T6_IE_MASK) 947 948 #define CTU_IR_T7_IE_MASK (0x8000U) 949 #define CTU_IR_T7_IE_SHIFT (15U) 950 #define CTU_IR_T7_IE_WIDTH (1U) 951 #define CTU_IR_T7_IE(x) (((uint16_t)(((uint16_t)(x)) << CTU_IR_T7_IE_SHIFT)) & CTU_IR_T7_IE_MASK) 952 /*! @} */ 953 954 /*! @name COTR - Control ON Time Register */ 955 /*! @{ */ 956 957 #define CTU_COTR_COTGT_MASK (0xFFU) 958 #define CTU_COTR_COTGT_SHIFT (0U) 959 #define CTU_COTR_COTGT_WIDTH (8U) 960 #define CTU_COTR_COTGT(x) (((uint16_t)(((uint16_t)(x)) << CTU_COTR_COTGT_SHIFT)) & CTU_COTR_COTGT_MASK) 961 /*! @} */ 962 963 /*! @name CR - Control Register */ 964 /*! @{ */ 965 966 #define CTU_CR_TGSISR_RE_MASK (0x1U) 967 #define CTU_CR_TGSISR_RE_SHIFT (0U) 968 #define CTU_CR_TGSISR_RE_WIDTH (1U) 969 #define CTU_CR_TGSISR_RE(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_TGSISR_RE_SHIFT)) & CTU_CR_TGSISR_RE_MASK) 970 971 #define CTU_CR_GRE_MASK (0x2U) 972 #define CTU_CR_GRE_SHIFT (1U) 973 #define CTU_CR_GRE_WIDTH (1U) 974 #define CTU_CR_GRE(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_GRE_SHIFT)) & CTU_CR_GRE_MASK) 975 976 #define CTU_CR_MRS_SG_MASK (0x4U) 977 #define CTU_CR_MRS_SG_SHIFT (2U) 978 #define CTU_CR_MRS_SG_WIDTH (1U) 979 #define CTU_CR_MRS_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_MRS_SG_SHIFT)) & CTU_CR_MRS_SG_MASK) 980 981 #define CTU_CR_FGRE_MASK (0x8U) 982 #define CTU_CR_FGRE_SHIFT (3U) 983 #define CTU_CR_FGRE_WIDTH (1U) 984 #define CTU_CR_FGRE(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_FGRE_SHIFT)) & CTU_CR_FGRE_MASK) 985 986 #define CTU_CR_CGRE_MASK (0x10U) 987 #define CTU_CR_CGRE_SHIFT (4U) 988 #define CTU_CR_CGRE_WIDTH (1U) 989 #define CTU_CR_CGRE(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_CGRE_SHIFT)) & CTU_CR_CGRE_MASK) 990 991 #define CTU_CR_DFE_MASK (0x20U) 992 #define CTU_CR_DFE_SHIFT (5U) 993 #define CTU_CR_DFE_WIDTH (1U) 994 #define CTU_CR_DFE(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_DFE_SHIFT)) & CTU_CR_DFE_MASK) 995 996 #define CTU_CR_CTU_ODIS_MASK (0x40U) 997 #define CTU_CR_CTU_ODIS_SHIFT (6U) 998 #define CTU_CR_CTU_ODIS_WIDTH (1U) 999 #define CTU_CR_CTU_ODIS(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_CTU_ODIS_SHIFT)) & CTU_CR_CTU_ODIS_MASK) 1000 1001 #define CTU_CR_CTU_ADC_R_MASK (0x80U) 1002 #define CTU_CR_CTU_ADC_R_SHIFT (7U) 1003 #define CTU_CR_CTU_ADC_R_WIDTH (1U) 1004 #define CTU_CR_CTU_ADC_R(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_CTU_ADC_R_SHIFT)) & CTU_CR_CTU_ADC_R_MASK) 1005 1006 #define CTU_CR_T0_SG_MASK (0x100U) 1007 #define CTU_CR_T0_SG_SHIFT (8U) 1008 #define CTU_CR_T0_SG_WIDTH (1U) 1009 #define CTU_CR_T0_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T0_SG_SHIFT)) & CTU_CR_T0_SG_MASK) 1010 1011 #define CTU_CR_T1_SG_MASK (0x200U) 1012 #define CTU_CR_T1_SG_SHIFT (9U) 1013 #define CTU_CR_T1_SG_WIDTH (1U) 1014 #define CTU_CR_T1_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T1_SG_SHIFT)) & CTU_CR_T1_SG_MASK) 1015 1016 #define CTU_CR_T2_SG_MASK (0x400U) 1017 #define CTU_CR_T2_SG_SHIFT (10U) 1018 #define CTU_CR_T2_SG_WIDTH (1U) 1019 #define CTU_CR_T2_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T2_SG_SHIFT)) & CTU_CR_T2_SG_MASK) 1020 1021 #define CTU_CR_T3_SG_MASK (0x800U) 1022 #define CTU_CR_T3_SG_SHIFT (11U) 1023 #define CTU_CR_T3_SG_WIDTH (1U) 1024 #define CTU_CR_T3_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T3_SG_SHIFT)) & CTU_CR_T3_SG_MASK) 1025 1026 #define CTU_CR_T4_SG_MASK (0x1000U) 1027 #define CTU_CR_T4_SG_SHIFT (12U) 1028 #define CTU_CR_T4_SG_WIDTH (1U) 1029 #define CTU_CR_T4_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T4_SG_SHIFT)) & CTU_CR_T4_SG_MASK) 1030 1031 #define CTU_CR_T5_SG_MASK (0x2000U) 1032 #define CTU_CR_T5_SG_SHIFT (13U) 1033 #define CTU_CR_T5_SG_WIDTH (1U) 1034 #define CTU_CR_T5_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T5_SG_SHIFT)) & CTU_CR_T5_SG_MASK) 1035 1036 #define CTU_CR_T6_SG_MASK (0x4000U) 1037 #define CTU_CR_T6_SG_SHIFT (14U) 1038 #define CTU_CR_T6_SG_WIDTH (1U) 1039 #define CTU_CR_T6_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T6_SG_SHIFT)) & CTU_CR_T6_SG_MASK) 1040 1041 #define CTU_CR_T7_SG_MASK (0x8000U) 1042 #define CTU_CR_T7_SG_SHIFT (15U) 1043 #define CTU_CR_T7_SG_WIDTH (1U) 1044 #define CTU_CR_T7_SG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CR_T7_SG_SHIFT)) & CTU_CR_T7_SG_MASK) 1045 /*! @} */ 1046 1047 /*! @name DFR - Digital Filter Register */ 1048 /*! @{ */ 1049 1050 #define CTU_DFR_FILTER_N_MASK (0xFFU) 1051 #define CTU_DFR_FILTER_N_SHIFT (0U) 1052 #define CTU_DFR_FILTER_N_WIDTH (8U) 1053 #define CTU_DFR_FILTER_N(x) (((uint16_t)(((uint16_t)(x)) << CTU_DFR_FILTER_N_SHIFT)) & CTU_DFR_FILTER_N_MASK) 1054 /*! @} */ 1055 1056 /*! @name EXPAR - Expected Value A Register */ 1057 /*! @{ */ 1058 1059 #define CTU_EXPAR_EXPA_MASK (0xFFFFU) 1060 #define CTU_EXPAR_EXPA_SHIFT (0U) 1061 #define CTU_EXPAR_EXPA_WIDTH (16U) 1062 #define CTU_EXPAR_EXPA(x) (((uint16_t)(((uint16_t)(x)) << CTU_EXPAR_EXPA_SHIFT)) & CTU_EXPAR_EXPA_MASK) 1063 /*! @} */ 1064 1065 /*! @name EXPBR - Expected Value B Register */ 1066 /*! @{ */ 1067 1068 #define CTU_EXPBR_EXPB_MASK (0xFFFFU) 1069 #define CTU_EXPBR_EXPB_SHIFT (0U) 1070 #define CTU_EXPBR_EXPB_WIDTH (16U) 1071 #define CTU_EXPBR_EXPB(x) (((uint16_t)(((uint16_t)(x)) << CTU_EXPBR_EXPB_SHIFT)) & CTU_EXPBR_EXPB_MASK) 1072 /*! @} */ 1073 1074 /*! @name CNTRNGR - Counter Range Register */ 1075 /*! @{ */ 1076 1077 #define CTU_CNTRNGR_CNTRNG_MASK (0xFFU) 1078 #define CTU_CNTRNGR_CNTRNG_SHIFT (0U) 1079 #define CTU_CNTRNGR_CNTRNG_WIDTH (8U) 1080 #define CTU_CNTRNGR_CNTRNG(x) (((uint16_t)(((uint16_t)(x)) << CTU_CNTRNGR_CNTRNG_SHIFT)) & CTU_CNTRNGR_CNTRNG_MASK) 1081 /*! @} */ 1082 1083 /*! @name LISTCSR - List Control/Status Register */ 1084 /*! @{ */ 1085 1086 #define CTU_LISTCSR_PAR_LIST_MASK (0x1U) 1087 #define CTU_LISTCSR_PAR_LIST_SHIFT (0U) 1088 #define CTU_LISTCSR_PAR_LIST_WIDTH (1U) 1089 #define CTU_LISTCSR_PAR_LIST(x) (((uint32_t)(((uint32_t)(x)) << CTU_LISTCSR_PAR_LIST_SHIFT)) & CTU_LISTCSR_PAR_LIST_MASK) 1090 1091 #define CTU_LISTCSR_LIST0_ADDR_MASK (0x1F0000U) 1092 #define CTU_LISTCSR_LIST0_ADDR_SHIFT (16U) 1093 #define CTU_LISTCSR_LIST0_ADDR_WIDTH (5U) 1094 #define CTU_LISTCSR_LIST0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTU_LISTCSR_LIST0_ADDR_SHIFT)) & CTU_LISTCSR_LIST0_ADDR_MASK) 1095 1096 #define CTU_LISTCSR_LIST0_BLK_MASK (0x800000U) 1097 #define CTU_LISTCSR_LIST0_BLK_SHIFT (23U) 1098 #define CTU_LISTCSR_LIST0_BLK_WIDTH (1U) 1099 #define CTU_LISTCSR_LIST0_BLK(x) (((uint32_t)(((uint32_t)(x)) << CTU_LISTCSR_LIST0_BLK_SHIFT)) & CTU_LISTCSR_LIST0_BLK_MASK) 1100 1101 #define CTU_LISTCSR_LIST1_ADDR_MASK (0x1F000000U) 1102 #define CTU_LISTCSR_LIST1_ADDR_SHIFT (24U) 1103 #define CTU_LISTCSR_LIST1_ADDR_WIDTH (5U) 1104 #define CTU_LISTCSR_LIST1_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CTU_LISTCSR_LIST1_ADDR_SHIFT)) & CTU_LISTCSR_LIST1_ADDR_MASK) 1105 1106 #define CTU_LISTCSR_LIST1_BLK_MASK (0x80000000U) 1107 #define CTU_LISTCSR_LIST1_BLK_SHIFT (31U) 1108 #define CTU_LISTCSR_LIST1_BLK_WIDTH (1U) 1109 #define CTU_LISTCSR_LIST1_BLK(x) (((uint32_t)(((uint32_t)(x)) << CTU_LISTCSR_LIST1_BLK_SHIFT)) & CTU_LISTCSR_LIST1_BLK_MASK) 1110 /*! @} */ 1111 1112 /*! 1113 * @} 1114 */ /* end of group CTU_Register_Masks */ 1115 1116 /*! 1117 * @} 1118 */ /* end of group CTU_Peripheral_Access_Layer */ 1119 1120 #endif /* #if !defined(S32Z2_CTU_H_) */ 1121
