| /hal_nxp-latest/imx/devices/MCIMX7D/ |
| D | MCIMX7D_M4.h | 799 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status … member 850 #define APBH_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) 20042 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, o… member 20091 #define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) 28052 …__IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offs… member 28155 #define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG)
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| /hal_nxp-latest/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 14050 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, o… member 14103 #define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) 23911 …__IO uint32_t CTRL1_TOG; /**< eLCDIF General Control1 Register, offs… member 24014 #define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG)
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/ |
| D | MIMX8MN5_cm7.h | 1607 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31704 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37216 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/ |
| D | MIMX8MN2_cm7.h | 1605 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31702 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37214 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/ |
| D | MIMX8MN4_cm7.h | 1605 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31702 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37214 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/ |
| D | MIMX8MN3_cm7.h | 1607 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31704 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37216 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/ |
| D | MIMX8MN1_cm7.h | 1607 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31704 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37216 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/ |
| D | MIMX8MN6_cm7.h | 1605 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31702 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37214 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| D | MIMX8MN6_ca53.h | 1634 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 31730 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37228 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/ |
| D | MIMX8MQ5_cm4.h | 1203 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 29258 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 36048 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/ |
| D | MIMX8MD7_cm4.h | 1203 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 29258 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 36048 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/ |
| D | MIMX8MD6_cm4.h | 1203 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 29258 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 36048 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/ |
| D | MIMX8MQ6_cm4.h | 1203 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 29258 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 36048 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/ |
| D | MIMX8MQ7_cm4.h | 1203 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 29258 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 36048 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/ |
| D | MIMX8MM3_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/ |
| D | MIMX8MM5_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/ |
| D | MIMX8MM6_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| D | MIMX8MM6_ca53.h | 1667 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33877 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37926 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/ |
| D | MIMX8MM1_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/ |
| D | MIMX8MM2_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/ |
| D | MIMX8MM4_cm4.h | 1637 …__IO uint32_t CTRL1_TOG; /**< AHB to APBH Bridge Control and Status Regist… member 33854 …__IO uint32_t CTRL1_TOG; /**< GPMI Control Register 1 Description, offset:… member 37917 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 10192 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 10193 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/ |
| D | MIMXRT1166_cm4.h | 53348 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member 78120 …__IO uint32_t CTRL1_TOG; /**< Temperature Sensor Control Register 1, offse… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/ |
| D | MIMXRT1173_cm4.h | 53875 …__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1… member 78619 …__IO uint32_t CTRL1_TOG; /**< Temperature Sensor Control Register 1, offse… member
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