Home
last modified time | relevance | path

Searched refs:CTRL1_SET (Results 1 – 25 of 69) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/drivers/elcdif/
Dfsl_elcdif.h416 base->CTRL1_SET = LCDIF_CTRL1_RESET_MASK; in ELCDIF_PullUpResetPin()
544 base->CTRL1_SET = (mask & ELCDIF_CTRL1_IRQ_EN_MASK); in ELCDIF_EnableInterrupts()
/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h797 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status … member
848 #define APBH_CTRL1_SET_REG(base) ((base)->CTRL1_SET)
20040 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, o… member
20089 #define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET)
28050 …__IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offs… member
28153 #define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET)
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h14048 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, o… member
14101 #define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET)
23909 …__IO uint32_t CTRL1_SET; /**< eLCDIF General Control1 Register, offs… member
24012 #define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h1605 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31702 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37214 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h1603 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31700 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37212 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h1603 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31700 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37212 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
DMIMX8MN6_ca53.h1632 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31728 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37226 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h1605 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31702 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37214 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h1603 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31700 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37212 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h1201 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
29256 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
36046 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h1605 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
31702 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37214 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h1201 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
29256 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
36046 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h1201 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
29256 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
36046 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h1201 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
29256 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
36046 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h1201 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
29256 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
36046 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
DMIMX8MM6_ca53.h1665 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33875 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37924 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h1635 …__IO uint32_t CTRL1_SET; /**< AHB to APBH Bridge Control and Status Regist… member
33852 …__IO uint32_t CTRL1_SET; /**< GPMI Control Register 1 Description, offset:… member
37915 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/
DMCIMX7U3_cm4.h10190 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/
DMCIMX7U5_cm4.h10191 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/
DMIMXRT1173_cm7.h53876 …__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x1… member
77715 …__IO uint32_t CTRL1_SET; /**< Temperature Sensor Control Register 1, offse… member

123