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Searched refs:CTRL0_TOG (Results 1 – 25 of 41) sorted by relevance

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/hal_nxp-latest/imx/devices/MCIMX7D/
DMCIMX7D_M4.h795 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status … member
846 #define APBH_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG)
20026 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, o… member
20079 #define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h1603 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31688 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h1601 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31686 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_cm7.h1601 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31686 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
DMIMX8MN6_ca53.h1630 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31714 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h1603 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31688 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h1601 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31686 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h1199 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
29242 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h1603 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
31688 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h1199 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
29242 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h1199 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
29242 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/imx/devices/MCIMX6X/
DMCIMX6X_M4.h14034 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, o… member
14091 #define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h1199 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
29242 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h1199 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
29242 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM1/
DMIMX8MM1_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM2/
DMIMX8MM2_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM6/
DMIMX8MM6_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
DMIMX8MM6_ca53.h1663 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33861 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM5/
DMIMX8MM5_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM4/
DMIMX8MM4_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8MM3/
DMIMX8MM3_cm4.h1633 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
33838 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML8/
DMIMX8ML8_dsp.h1775 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
50415 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
DMIMX8ML8_cm7.h1792 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
52528 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML4/
DMIMX8ML4_cm7.h1792 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
52528 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8ML6/
DMIMX8ML6_cm7.h1792 …__IO uint32_t CTRL0_TOG; /**< AHB to APBH Bridge Control and Status Regist… member
52528 …__IO uint32_t CTRL0_TOG; /**< GPMI Control Register 0 Description, offset:… member

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