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Searched refs:CTRL0 (Results 1 – 25 of 154) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1182/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
325 VMBANDGAP->CTRL0.SET = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_DisableBandgapSelfBiasAfterPowerUp()
336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1181/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
325 VMBANDGAP->CTRL0.SET = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_DisableBandgapSelfBiasAfterPowerUp()
336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1189/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
325 VMBANDGAP->CTRL0.SET = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_DisableBandgapSelfBiasAfterPowerUp()
336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1187/drivers/
Dfsl_pmu.c85 temp32 = PHY_LDO->CTRL0.RW; in PMU_StaticEnablePllLdo()
90 PHY_LDO->CTRL0.RW = in PMU_StaticEnablePllLdo()
94 PHY_LDO->CTRL0.RW &= ~PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK; in PMU_StaticEnablePllLdo()
103 PHY_LDO->CTRL0.RW = 0UL; in PMU_StaticDisablePllLdo()
325 VMBANDGAP->CTRL0.SET = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_DisableBandgapSelfBiasAfterPowerUp()
336 VMBANDGAP->CTRL0.CLR = VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK; in PMU_EnableBandgapSelfBiasBeforePowerDown()
350 temp32 = VMBANDGAP->CTRL0.RW; in PMU_StaticBandgapInit()
358 VMBANDGAP->CTRL0.RW = temp32; in PMU_StaticBandgapInit()
Dfsl_clock.c609 base->CTRL0.SET = PLL_CTRL0_POWERUP_MASK | PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllSetPower()
613 base->CTRL0.CLR = PLL_CTRL0_POWERUP_MASK; in ANATOP_PllSetPower()
621 base->CTRL0.SET = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
625 base->CTRL0.CLR = PLL_CTRL0_BYPASS_MASK; in ANATOP_PllBypass()
633 base->CTRL0.SET = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
637 base->CTRL0.CLR = PLL_CTRL0_PLL_REG_EN_MASK; in ANATOP_PllEnablePllReg()
645 base->CTRL0.SET = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
649 base->CTRL0.CLR = PLL_CTRL0_HOLD_RING_OFF_MASK; in ANATOP_PllHoldRingOff()
664 base->CTRL0.SET = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
668 base->CTRL0.CLR = PLL_CTRL0_ENABLE_MASK; in ANATOP_PllEnableSs()
[all …]
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK; in DCDC_Deinit()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/drivers/
Dfsl_dcdc.h504 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
508 base->CTRL0 &= ~DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerModeViaStandbyRequest()
525 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
529 base->CTRL0 &= ~DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
544 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
548 base->CTRL0 &= ~DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterStandbyMode()
/hal_nxp-latest/mcux/mcux-sdk/drivers/xbar/
Dfsl_xbar.c21 #define XBAR_CTRLx(base, index) (((volatile uint16_t *)(&((base)->CTRL0)))[(index)])
162 status_flag = (uint32_t)base->CTRL0 & XBAR_CTRL_STS_MASK; in XBAR_GetStatusFlags()
181 regVal = (base->CTRL0); in XBAR_ClearStatusFlags()
188 base->CTRL0 = regVal; in XBAR_ClearStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/drivers/xbara/
Dfsl_xbara.c21 #define XBARA_CTRLx(base, index) (((volatile uint16_t *)(&((base)->CTRL0)))[(index)])
152 status_flag = ((uint32_t)base->CTRL0 & (XBARA_CTRL0_STS0_MASK | XBARA_CTRL0_STS1_MASK)); in XBARA_GetStatusFlags()
170 regVal = (base->CTRL0); in XBARA_ClearStatusFlags()
176 base->CTRL0 = regVal; in XBARA_ClearStatusFlags()
/hal_nxp-latest/mcux/mcux-sdk/drivers/cns_acomp/
Dfsl_acomp.c92 tmp32 = ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)config->id); in ACOMP_Init()
105 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)config->id) = tmp32; in ACOMP_Init()
189 tmp32 = ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id); in ACOMP_SetInputConfig()
198 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) = tmp32; in ACOMP_SetInputConfig()
Dfsl_acomp.h355 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) |= ACOMP_CTRL1_MUXEN_MASK; in ACOMP_Enable()
356 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) |= ACOMP_CTRL1_EN_MASK; in ACOMP_Enable()
360 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) &= ~ACOMP_CTRL1_MUXEN_MASK; in ACOMP_Enable()
361 ACOMP_GET_REG_VAL(&(base->CTRL0), (uint8_t)id) &= ~ACOMP_CTRL1_EN_MASK; in ACOMP_Enable()
/hal_nxp-latest/mcux/mcux-sdk/drivers/dcdc_1/
Dfsl_dcdc.c98 uint32_t tmp32 = base->CTRL0; in DCDC_Init()
110 base->CTRL0 |= DCDC_CTRL0_ENABLE_MASK; in DCDC_Init()
111 base->CTRL0 = tmp32; in DCDC_Init()
179 base->CTRL0 |= DCDC_CTRL0_STBY_EN_MASK; in DCDC_EnterLowPowerMode()
182 base->CTRL0 |= DCDC_CTRL0_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()
185 base->CTRL0 |= DCDC_CTRL0_STBY_LP_MODE_EN_MASK; in DCDC_EnterLowPowerMode()

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