| /hal_nxp-latest/mcux/mcux-sdk/drivers/otfad/ |
| D | fsl_otfad.c | 181 base->CTX[contextIndex].CTR[0] = tempCounter[0]; in OTFAD_SetEncryptionConfig()
182 base->CTX[contextIndex].CTR[1] = tempCounter[1]; in OTFAD_SetEncryptionConfig()
210 config->counter[0] = base->CTX[config->contextIndex].CTR[0]; in OTFAD_GetEncryptionConfig()
211 config->counter[1] = base->CTX[config->contextIndex].CTR[1]; in OTFAD_GetEncryptionConfig()
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32XX.h | 143 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex)) macro
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| D | Adc_Sar_Ip_HeaderWrapper_S32XX_AE.h | 138 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex)) macro
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/include/ |
| D | Adc_Sar_Ip_HeaderWrapper_S32K3.h | 173 #define CTR(base, regIndex) REG_ACCESS((base)->CTR0, (regIndex)) macro
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| /hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/ |
| D | S32Z2_SCB.h | 107 __I uint32_t CTR; /**< Cache Type Register, offset: 0xD7C */ member
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| /hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/ |
| D | S32K344_SCB.h | 106 __I uint32_t CTR; /**< Cache Type Register, offset: 0xD7C */ member
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Core/Include/ |
| D | core_cm7.h | 483 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| D | core_cm33.h | 526 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /hal_nxp-latest/mcux/mcux-sdk/CMSIS/Include/ |
| D | core_armv8mml.h | 519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| D | core_cm35p.h | 519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| D | core_cm7.h | 478 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| D | core_cm33.h | 519 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| D | core_armv81mml.h | 520 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ member
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| /hal_nxp-latest/s32/drivers/s32ze/Adc/src/ |
| D | Adc_Sar_Ip.c | 4167 CTR(AdcAEBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]); in Adc_Sar_Ip_SetSampleTimes()
4177 CTR(AdcBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]); in Adc_Sar_Ip_SetSampleTimes()
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| /hal_nxp-latest/s32/drivers/s32k3/Adc/src/ |
| D | Adc_Sar_Ip.c | 3929 CTR(AdcAEBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]); in Adc_Sar_Ip_SetSampleTimes()
3939 CTR(AdcBasePtr, Index) = ADC_CTR_INPSAMP(aSampleTimes[Index]); in Adc_Sar_Ip_SetSampleTimes()
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/ |
| D | MIMXRT685S_dsp.h | 16650 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| D | MIMXRT685S_cm33.h | 23568 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/ |
| D | MCIMX7U3_cm4.h | 22193 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0x110, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/ |
| D | MCIMX7U5_cm4.h | 22194 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0x110, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 21800 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/ |
| D | MIMXRT633S.h | 23568 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/ |
| D | MIMXRT595S_dsp.h | 27871 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| D | MIMXRT595S_cm33.h | 35059 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/ |
| D | MIMXRT533S.h | 33432 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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| /hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/ |
| D | MIMXRT555S.h | 35058 …__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array… member
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