1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CSTCU.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CSTCU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CSTCU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CSTCU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CSTCU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CSTCU_Peripheral_Access_Layer CSTCU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CSTCU - Size of Registers Arrays */ 72 #define CSTCU_LRFSTAT_COUNT 1u 73 #define CSTCU_LUFSTAT_COUNT 1u 74 #define CSTCU_BYPLSTCU_COUNT 1u 75 #define CSTCU_LSTCU_MBSCH_COUNT 20u 76 #define CSTCU_LSTCU_LBSCH_COUNT 20u 77 78 /** CSTCU - Register Layout Typedef */ 79 typedef struct { 80 __IO uint32_t RUNSWREG; /**< Run Software, offset: 0x0 */ 81 __IO uint32_t LSCHLVLD; /**< LSTCU Scheduler List Valid, offset: 0x4 */ 82 uint8_t RESERVED_0[4]; 83 __IO uint32_t WDG; /**< Watchdog Timer, offset: 0xC */ 84 __IO uint32_t IE; /**< Interrupt Enable, offset: 0x10 */ 85 __IO uint32_t IF; /**< Interrupt Flag, offset: 0x14 */ 86 uint8_t RESERVED_1[8]; 87 __IO uint32_t ERR_STAT; /**< Error Status, offset: 0x20 */ 88 uint8_t RESERVED_2[4]; 89 __IO uint32_t ERR_FM; /**< Error Fault Mapping, offset: 0x28 */ 90 uint8_t RESERVED_3[4]; 91 __I uint32_t LRFSTAT[CSTCU_LRFSTAT_COUNT]; /**< LSTCU Recoverable Fault Status, array offset: 0x30, array step: 0x4 */ 92 uint8_t RESERVED_4[12]; 93 __I uint32_t LUFSTAT[CSTCU_LUFSTAT_COUNT]; /**< LSTCU Unrecoverable Fault Status, array offset: 0x40, array step: 0x4 */ 94 uint8_t RESERVED_5[12]; 95 __IO uint32_t RDEN; /**< Reset Domain Self-Test Enable, offset: 0x50 */ 96 __I uint32_t RDENSTAT; /**< Reset Domain Enable Status, offset: 0x54 */ 97 __I uint32_t LASTRDEN; /**< Last Run Reset Domain Enable, offset: 0x58 */ 98 uint8_t RESERVED_6[4]; 99 __IO uint32_t BYPLSTCU[CSTCU_BYPLSTCU_COUNT]; /**< Bypass LSTCU, array offset: 0x60, array step: 0x4 */ 100 uint8_t RESERVED_7[12]; 101 __IO uint32_t STAG; /**< Stagger, offset: 0x70 */ 102 uint8_t RESERVED_8[396]; 103 __IO uint32_t LMBPTR[CSTCU_LSTCU_MBSCH_COUNT]; /**< LSTCU MBIST Run Phase Scheduler Pointer, array offset: 0x200, array step: 0x4 */ 104 uint8_t RESERVED_9[176]; 105 __IO uint32_t LLBPTR[CSTCU_LSTCU_LBSCH_COUNT]; /**< LSTCU LBIST Run phase Scheduler Pointer, array offset: 0x300, array step: 0x4 */ 106 } CSTCU_Type, *CSTCU_MemMapPtr; 107 108 /** Number of instances of the CSTCU module. */ 109 #define CSTCU_INSTANCE_COUNT (1u) 110 111 /* CSTCU - Peripheral instance base addresses */ 112 /** Peripheral CSTCU base address */ 113 #define IP_CSTCU_BASE (0x41910000u) 114 /** Peripheral CSTCU base pointer */ 115 #define IP_CSTCU ((CSTCU_Type *)IP_CSTCU_BASE) 116 /** Array initializer of CSTCU peripheral base addresses */ 117 #define IP_CSTCU_BASE_ADDRS { IP_CSTCU_BASE } 118 /** Array initializer of CSTCU peripheral base pointers */ 119 #define IP_CSTCU_BASE_PTRS { IP_CSTCU } 120 121 /* ---------------------------------------------------------------------------- 122 -- CSTCU Register Masks 123 ---------------------------------------------------------------------------- */ 124 125 /*! 126 * @addtogroup CSTCU_Register_Masks CSTCU Register Masks 127 * @{ 128 */ 129 130 /*! @name RUNSWREG - Run Software */ 131 /*! @{ */ 132 133 #define CSTCU_RUNSWREG_RUNSW_MASK (0x1U) 134 #define CSTCU_RUNSWREG_RUNSW_SHIFT (0U) 135 #define CSTCU_RUNSWREG_RUNSW_WIDTH (1U) 136 #define CSTCU_RUNSWREG_RUNSW(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RUNSWREG_RUNSW_SHIFT)) & CSTCU_RUNSWREG_RUNSW_MASK) 137 /*! @} */ 138 139 /*! @name LSCHLVLD - LSTCU Scheduler List Valid */ 140 /*! @{ */ 141 142 #define CSTCU_LSCHLVLD_MBPLVLD_MASK (0x100U) 143 #define CSTCU_LSCHLVLD_MBPLVLD_SHIFT (8U) 144 #define CSTCU_LSCHLVLD_MBPLVLD_WIDTH (1U) 145 #define CSTCU_LSCHLVLD_MBPLVLD(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LSCHLVLD_MBPLVLD_SHIFT)) & CSTCU_LSCHLVLD_MBPLVLD_MASK) 146 147 #define CSTCU_LSCHLVLD_LBPLVLD_MASK (0x10000U) 148 #define CSTCU_LSCHLVLD_LBPLVLD_SHIFT (16U) 149 #define CSTCU_LSCHLVLD_LBPLVLD_WIDTH (1U) 150 #define CSTCU_LSCHLVLD_LBPLVLD(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LSCHLVLD_LBPLVLD_SHIFT)) & CSTCU_LSCHLVLD_LBPLVLD_MASK) 151 /*! @} */ 152 153 /*! @name WDG - Watchdog Timer */ 154 /*! @{ */ 155 156 #define CSTCU_WDG_WDGEOC_MASK (0xFFFFFFFFU) 157 #define CSTCU_WDG_WDGEOC_SHIFT (0U) 158 #define CSTCU_WDG_WDGEOC_WIDTH (32U) 159 #define CSTCU_WDG_WDGEOC(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_WDG_WDGEOC_SHIFT)) & CSTCU_WDG_WDGEOC_MASK) 160 /*! @} */ 161 162 /*! @name IE - Interrupt Enable */ 163 /*! @{ */ 164 165 #define CSTCU_IE_STEND_IE_MASK (0x1U) 166 #define CSTCU_IE_STEND_IE_SHIFT (0U) 167 #define CSTCU_IE_STEND_IE_WIDTH (1U) 168 #define CSTCU_IE_STEND_IE(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_IE_STEND_IE_SHIFT)) & CSTCU_IE_STEND_IE_MASK) 169 /*! @} */ 170 171 /*! @name IF - Interrupt Flag */ 172 /*! @{ */ 173 174 #define CSTCU_IF_STEND_IF_MASK (0x1U) 175 #define CSTCU_IF_STEND_IF_SHIFT (0U) 176 #define CSTCU_IF_STEND_IF_WIDTH (1U) 177 #define CSTCU_IF_STEND_IF(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_IF_STEND_IF_SHIFT)) & CSTCU_IF_STEND_IF_MASK) 178 /*! @} */ 179 180 /*! @name ERR_STAT - Error Status */ 181 /*! @{ */ 182 183 #define CSTCU_ERR_STAT_INVP_MB_MASK (0x2U) 184 #define CSTCU_ERR_STAT_INVP_MB_SHIFT (1U) 185 #define CSTCU_ERR_STAT_INVP_MB_WIDTH (1U) 186 #define CSTCU_ERR_STAT_INVP_MB(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_STAT_INVP_MB_SHIFT)) & CSTCU_ERR_STAT_INVP_MB_MASK) 187 188 #define CSTCU_ERR_STAT_INVP_LB_MASK (0x4U) 189 #define CSTCU_ERR_STAT_INVP_LB_SHIFT (2U) 190 #define CSTCU_ERR_STAT_INVP_LB_WIDTH (1U) 191 #define CSTCU_ERR_STAT_INVP_LB(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_STAT_INVP_LB_SHIFT)) & CSTCU_ERR_STAT_INVP_LB_MASK) 192 193 #define CSTCU_ERR_STAT_ABORTHW_MASK (0x100U) 194 #define CSTCU_ERR_STAT_ABORTHW_SHIFT (8U) 195 #define CSTCU_ERR_STAT_ABORTHW_WIDTH (1U) 196 #define CSTCU_ERR_STAT_ABORTHW(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_STAT_ABORTHW_SHIFT)) & CSTCU_ERR_STAT_ABORTHW_MASK) 197 198 #define CSTCU_ERR_STAT_UFSF_MASK (0x10000U) 199 #define CSTCU_ERR_STAT_UFSF_SHIFT (16U) 200 #define CSTCU_ERR_STAT_UFSF_WIDTH (1U) 201 #define CSTCU_ERR_STAT_UFSF(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_STAT_UFSF_SHIFT)) & CSTCU_ERR_STAT_UFSF_MASK) 202 203 #define CSTCU_ERR_STAT_RFSF_MASK (0x20000U) 204 #define CSTCU_ERR_STAT_RFSF_SHIFT (17U) 205 #define CSTCU_ERR_STAT_RFSF_WIDTH (1U) 206 #define CSTCU_ERR_STAT_RFSF(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_STAT_RFSF_SHIFT)) & CSTCU_ERR_STAT_RFSF_MASK) 207 /*! @} */ 208 209 /*! @name ERR_FM - Error Fault Mapping */ 210 /*! @{ */ 211 212 #define CSTCU_ERR_FM_INVPFMMB_MASK (0x2U) 213 #define CSTCU_ERR_FM_INVPFMMB_SHIFT (1U) 214 #define CSTCU_ERR_FM_INVPFMMB_WIDTH (1U) 215 #define CSTCU_ERR_FM_INVPFMMB(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_FM_INVPFMMB_SHIFT)) & CSTCU_ERR_FM_INVPFMMB_MASK) 216 217 #define CSTCU_ERR_FM_INVPFMLB_MASK (0x4U) 218 #define CSTCU_ERR_FM_INVPFMLB_SHIFT (2U) 219 #define CSTCU_ERR_FM_INVPFMLB_WIDTH (1U) 220 #define CSTCU_ERR_FM_INVPFMLB(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_ERR_FM_INVPFMLB_SHIFT)) & CSTCU_ERR_FM_INVPFMLB_MASK) 221 /*! @} */ 222 223 /*! @name LRFSTAT - LSTCU Recoverable Fault Status */ 224 /*! @{ */ 225 226 #define CSTCU_LRFSTAT_RFSLSTCU0_MASK (0x1U) 227 #define CSTCU_LRFSTAT_RFSLSTCU0_SHIFT (0U) 228 #define CSTCU_LRFSTAT_RFSLSTCU0_WIDTH (1U) 229 #define CSTCU_LRFSTAT_RFSLSTCU0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU0_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU0_MASK) 230 231 #define CSTCU_LRFSTAT_RFSLSTCU1_MASK (0x2U) 232 #define CSTCU_LRFSTAT_RFSLSTCU1_SHIFT (1U) 233 #define CSTCU_LRFSTAT_RFSLSTCU1_WIDTH (1U) 234 #define CSTCU_LRFSTAT_RFSLSTCU1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU1_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU1_MASK) 235 236 #define CSTCU_LRFSTAT_RFSLSTCU2_MASK (0x4U) 237 #define CSTCU_LRFSTAT_RFSLSTCU2_SHIFT (2U) 238 #define CSTCU_LRFSTAT_RFSLSTCU2_WIDTH (1U) 239 #define CSTCU_LRFSTAT_RFSLSTCU2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU2_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU2_MASK) 240 241 #define CSTCU_LRFSTAT_RFSLSTCU3_MASK (0x8U) 242 #define CSTCU_LRFSTAT_RFSLSTCU3_SHIFT (3U) 243 #define CSTCU_LRFSTAT_RFSLSTCU3_WIDTH (1U) 244 #define CSTCU_LRFSTAT_RFSLSTCU3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU3_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU3_MASK) 245 246 #define CSTCU_LRFSTAT_RFSLSTCU4_MASK (0x10U) 247 #define CSTCU_LRFSTAT_RFSLSTCU4_SHIFT (4U) 248 #define CSTCU_LRFSTAT_RFSLSTCU4_WIDTH (1U) 249 #define CSTCU_LRFSTAT_RFSLSTCU4(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU4_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU4_MASK) 250 251 #define CSTCU_LRFSTAT_RFSLSTCU5_MASK (0x20U) 252 #define CSTCU_LRFSTAT_RFSLSTCU5_SHIFT (5U) 253 #define CSTCU_LRFSTAT_RFSLSTCU5_WIDTH (1U) 254 #define CSTCU_LRFSTAT_RFSLSTCU5(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU5_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU5_MASK) 255 256 #define CSTCU_LRFSTAT_RFSLSTCU6_MASK (0x40U) 257 #define CSTCU_LRFSTAT_RFSLSTCU6_SHIFT (6U) 258 #define CSTCU_LRFSTAT_RFSLSTCU6_WIDTH (1U) 259 #define CSTCU_LRFSTAT_RFSLSTCU6(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU6_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU6_MASK) 260 261 #define CSTCU_LRFSTAT_RFSLSTCU7_MASK (0x80U) 262 #define CSTCU_LRFSTAT_RFSLSTCU7_SHIFT (7U) 263 #define CSTCU_LRFSTAT_RFSLSTCU7_WIDTH (1U) 264 #define CSTCU_LRFSTAT_RFSLSTCU7(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU7_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU7_MASK) 265 266 #define CSTCU_LRFSTAT_RFSLSTCU8_MASK (0x100U) 267 #define CSTCU_LRFSTAT_RFSLSTCU8_SHIFT (8U) 268 #define CSTCU_LRFSTAT_RFSLSTCU8_WIDTH (1U) 269 #define CSTCU_LRFSTAT_RFSLSTCU8(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU8_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU8_MASK) 270 271 #define CSTCU_LRFSTAT_RFSLSTCU9_MASK (0x200U) 272 #define CSTCU_LRFSTAT_RFSLSTCU9_SHIFT (9U) 273 #define CSTCU_LRFSTAT_RFSLSTCU9_WIDTH (1U) 274 #define CSTCU_LRFSTAT_RFSLSTCU9(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU9_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU9_MASK) 275 276 #define CSTCU_LRFSTAT_RFSLSTCU10_MASK (0x400U) 277 #define CSTCU_LRFSTAT_RFSLSTCU10_SHIFT (10U) 278 #define CSTCU_LRFSTAT_RFSLSTCU10_WIDTH (1U) 279 #define CSTCU_LRFSTAT_RFSLSTCU10(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU10_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU10_MASK) 280 281 #define CSTCU_LRFSTAT_RFSLSTCU11_MASK (0x800U) 282 #define CSTCU_LRFSTAT_RFSLSTCU11_SHIFT (11U) 283 #define CSTCU_LRFSTAT_RFSLSTCU11_WIDTH (1U) 284 #define CSTCU_LRFSTAT_RFSLSTCU11(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU11_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU11_MASK) 285 286 #define CSTCU_LRFSTAT_RFSLSTCU12_MASK (0x1000U) 287 #define CSTCU_LRFSTAT_RFSLSTCU12_SHIFT (12U) 288 #define CSTCU_LRFSTAT_RFSLSTCU12_WIDTH (1U) 289 #define CSTCU_LRFSTAT_RFSLSTCU12(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU12_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU12_MASK) 290 291 #define CSTCU_LRFSTAT_RFSLSTCU13_MASK (0x2000U) 292 #define CSTCU_LRFSTAT_RFSLSTCU13_SHIFT (13U) 293 #define CSTCU_LRFSTAT_RFSLSTCU13_WIDTH (1U) 294 #define CSTCU_LRFSTAT_RFSLSTCU13(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU13_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU13_MASK) 295 296 #define CSTCU_LRFSTAT_RFSLSTCU14_MASK (0x4000U) 297 #define CSTCU_LRFSTAT_RFSLSTCU14_SHIFT (14U) 298 #define CSTCU_LRFSTAT_RFSLSTCU14_WIDTH (1U) 299 #define CSTCU_LRFSTAT_RFSLSTCU14(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU14_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU14_MASK) 300 301 #define CSTCU_LRFSTAT_RFSLSTCU15_MASK (0x8000U) 302 #define CSTCU_LRFSTAT_RFSLSTCU15_SHIFT (15U) 303 #define CSTCU_LRFSTAT_RFSLSTCU15_WIDTH (1U) 304 #define CSTCU_LRFSTAT_RFSLSTCU15(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU15_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU15_MASK) 305 306 #define CSTCU_LRFSTAT_RFSLSTCU16_MASK (0x10000U) 307 #define CSTCU_LRFSTAT_RFSLSTCU16_SHIFT (16U) 308 #define CSTCU_LRFSTAT_RFSLSTCU16_WIDTH (1U) 309 #define CSTCU_LRFSTAT_RFSLSTCU16(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU16_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU16_MASK) 310 311 #define CSTCU_LRFSTAT_RFSLSTCU17_MASK (0x20000U) 312 #define CSTCU_LRFSTAT_RFSLSTCU17_SHIFT (17U) 313 #define CSTCU_LRFSTAT_RFSLSTCU17_WIDTH (1U) 314 #define CSTCU_LRFSTAT_RFSLSTCU17(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU17_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU17_MASK) 315 316 #define CSTCU_LRFSTAT_RFSLSTCU18_MASK (0x40000U) 317 #define CSTCU_LRFSTAT_RFSLSTCU18_SHIFT (18U) 318 #define CSTCU_LRFSTAT_RFSLSTCU18_WIDTH (1U) 319 #define CSTCU_LRFSTAT_RFSLSTCU18(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU18_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU18_MASK) 320 321 #define CSTCU_LRFSTAT_RFSLSTCU19_MASK (0x80000U) 322 #define CSTCU_LRFSTAT_RFSLSTCU19_SHIFT (19U) 323 #define CSTCU_LRFSTAT_RFSLSTCU19_WIDTH (1U) 324 #define CSTCU_LRFSTAT_RFSLSTCU19(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LRFSTAT_RFSLSTCU19_SHIFT)) & CSTCU_LRFSTAT_RFSLSTCU19_MASK) 325 /*! @} */ 326 327 /*! @name LUFSTAT - LSTCU Unrecoverable Fault Status */ 328 /*! @{ */ 329 330 #define CSTCU_LUFSTAT_UFSLSTCU0_MASK (0x1U) 331 #define CSTCU_LUFSTAT_UFSLSTCU0_SHIFT (0U) 332 #define CSTCU_LUFSTAT_UFSLSTCU0_WIDTH (1U) 333 #define CSTCU_LUFSTAT_UFSLSTCU0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU0_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU0_MASK) 334 335 #define CSTCU_LUFSTAT_UFSLSTCU1_MASK (0x2U) 336 #define CSTCU_LUFSTAT_UFSLSTCU1_SHIFT (1U) 337 #define CSTCU_LUFSTAT_UFSLSTCU1_WIDTH (1U) 338 #define CSTCU_LUFSTAT_UFSLSTCU1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU1_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU1_MASK) 339 340 #define CSTCU_LUFSTAT_UFSLSTCU2_MASK (0x4U) 341 #define CSTCU_LUFSTAT_UFSLSTCU2_SHIFT (2U) 342 #define CSTCU_LUFSTAT_UFSLSTCU2_WIDTH (1U) 343 #define CSTCU_LUFSTAT_UFSLSTCU2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU2_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU2_MASK) 344 345 #define CSTCU_LUFSTAT_UFSLSTCU3_MASK (0x8U) 346 #define CSTCU_LUFSTAT_UFSLSTCU3_SHIFT (3U) 347 #define CSTCU_LUFSTAT_UFSLSTCU3_WIDTH (1U) 348 #define CSTCU_LUFSTAT_UFSLSTCU3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU3_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU3_MASK) 349 350 #define CSTCU_LUFSTAT_UFSLSTCU4_MASK (0x10U) 351 #define CSTCU_LUFSTAT_UFSLSTCU4_SHIFT (4U) 352 #define CSTCU_LUFSTAT_UFSLSTCU4_WIDTH (1U) 353 #define CSTCU_LUFSTAT_UFSLSTCU4(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU4_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU4_MASK) 354 355 #define CSTCU_LUFSTAT_UFSLSTCU5_MASK (0x20U) 356 #define CSTCU_LUFSTAT_UFSLSTCU5_SHIFT (5U) 357 #define CSTCU_LUFSTAT_UFSLSTCU5_WIDTH (1U) 358 #define CSTCU_LUFSTAT_UFSLSTCU5(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU5_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU5_MASK) 359 360 #define CSTCU_LUFSTAT_UFSLSTCU6_MASK (0x40U) 361 #define CSTCU_LUFSTAT_UFSLSTCU6_SHIFT (6U) 362 #define CSTCU_LUFSTAT_UFSLSTCU6_WIDTH (1U) 363 #define CSTCU_LUFSTAT_UFSLSTCU6(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU6_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU6_MASK) 364 365 #define CSTCU_LUFSTAT_UFSLSTCU7_MASK (0x80U) 366 #define CSTCU_LUFSTAT_UFSLSTCU7_SHIFT (7U) 367 #define CSTCU_LUFSTAT_UFSLSTCU7_WIDTH (1U) 368 #define CSTCU_LUFSTAT_UFSLSTCU7(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU7_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU7_MASK) 369 370 #define CSTCU_LUFSTAT_UFSLSTCU8_MASK (0x100U) 371 #define CSTCU_LUFSTAT_UFSLSTCU8_SHIFT (8U) 372 #define CSTCU_LUFSTAT_UFSLSTCU8_WIDTH (1U) 373 #define CSTCU_LUFSTAT_UFSLSTCU8(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU8_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU8_MASK) 374 375 #define CSTCU_LUFSTAT_UFSLSTCU9_MASK (0x200U) 376 #define CSTCU_LUFSTAT_UFSLSTCU9_SHIFT (9U) 377 #define CSTCU_LUFSTAT_UFSLSTCU9_WIDTH (1U) 378 #define CSTCU_LUFSTAT_UFSLSTCU9(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU9_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU9_MASK) 379 380 #define CSTCU_LUFSTAT_UFSLSTCU10_MASK (0x400U) 381 #define CSTCU_LUFSTAT_UFSLSTCU10_SHIFT (10U) 382 #define CSTCU_LUFSTAT_UFSLSTCU10_WIDTH (1U) 383 #define CSTCU_LUFSTAT_UFSLSTCU10(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU10_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU10_MASK) 384 385 #define CSTCU_LUFSTAT_UFSLSTCU11_MASK (0x800U) 386 #define CSTCU_LUFSTAT_UFSLSTCU11_SHIFT (11U) 387 #define CSTCU_LUFSTAT_UFSLSTCU11_WIDTH (1U) 388 #define CSTCU_LUFSTAT_UFSLSTCU11(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU11_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU11_MASK) 389 390 #define CSTCU_LUFSTAT_UFSLSTCU12_MASK (0x1000U) 391 #define CSTCU_LUFSTAT_UFSLSTCU12_SHIFT (12U) 392 #define CSTCU_LUFSTAT_UFSLSTCU12_WIDTH (1U) 393 #define CSTCU_LUFSTAT_UFSLSTCU12(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU12_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU12_MASK) 394 395 #define CSTCU_LUFSTAT_UFSLSTCU13_MASK (0x2000U) 396 #define CSTCU_LUFSTAT_UFSLSTCU13_SHIFT (13U) 397 #define CSTCU_LUFSTAT_UFSLSTCU13_WIDTH (1U) 398 #define CSTCU_LUFSTAT_UFSLSTCU13(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU13_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU13_MASK) 399 400 #define CSTCU_LUFSTAT_UFSLSTCU14_MASK (0x4000U) 401 #define CSTCU_LUFSTAT_UFSLSTCU14_SHIFT (14U) 402 #define CSTCU_LUFSTAT_UFSLSTCU14_WIDTH (1U) 403 #define CSTCU_LUFSTAT_UFSLSTCU14(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU14_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU14_MASK) 404 405 #define CSTCU_LUFSTAT_UFSLSTCU15_MASK (0x8000U) 406 #define CSTCU_LUFSTAT_UFSLSTCU15_SHIFT (15U) 407 #define CSTCU_LUFSTAT_UFSLSTCU15_WIDTH (1U) 408 #define CSTCU_LUFSTAT_UFSLSTCU15(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU15_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU15_MASK) 409 410 #define CSTCU_LUFSTAT_UFSLSTCU16_MASK (0x10000U) 411 #define CSTCU_LUFSTAT_UFSLSTCU16_SHIFT (16U) 412 #define CSTCU_LUFSTAT_UFSLSTCU16_WIDTH (1U) 413 #define CSTCU_LUFSTAT_UFSLSTCU16(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU16_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU16_MASK) 414 415 #define CSTCU_LUFSTAT_UFSLSTCU17_MASK (0x20000U) 416 #define CSTCU_LUFSTAT_UFSLSTCU17_SHIFT (17U) 417 #define CSTCU_LUFSTAT_UFSLSTCU17_WIDTH (1U) 418 #define CSTCU_LUFSTAT_UFSLSTCU17(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU17_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU17_MASK) 419 420 #define CSTCU_LUFSTAT_UFSLSTCU18_MASK (0x40000U) 421 #define CSTCU_LUFSTAT_UFSLSTCU18_SHIFT (18U) 422 #define CSTCU_LUFSTAT_UFSLSTCU18_WIDTH (1U) 423 #define CSTCU_LUFSTAT_UFSLSTCU18(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU18_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU18_MASK) 424 425 #define CSTCU_LUFSTAT_UFSLSTCU19_MASK (0x80000U) 426 #define CSTCU_LUFSTAT_UFSLSTCU19_SHIFT (19U) 427 #define CSTCU_LUFSTAT_UFSLSTCU19_WIDTH (1U) 428 #define CSTCU_LUFSTAT_UFSLSTCU19(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LUFSTAT_UFSLSTCU19_SHIFT)) & CSTCU_LUFSTAT_UFSLSTCU19_MASK) 429 /*! @} */ 430 431 /*! @name RDEN - Reset Domain Self-Test Enable */ 432 /*! @{ */ 433 434 #define CSTCU_RDEN_SERD0_MASK (0x1U) 435 #define CSTCU_RDEN_SERD0_SHIFT (0U) 436 #define CSTCU_RDEN_SERD0_WIDTH (1U) 437 #define CSTCU_RDEN_SERD0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDEN_SERD0_SHIFT)) & CSTCU_RDEN_SERD0_MASK) 438 439 #define CSTCU_RDEN_SERD1_MASK (0x2U) 440 #define CSTCU_RDEN_SERD1_SHIFT (1U) 441 #define CSTCU_RDEN_SERD1_WIDTH (1U) 442 #define CSTCU_RDEN_SERD1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDEN_SERD1_SHIFT)) & CSTCU_RDEN_SERD1_MASK) 443 444 #define CSTCU_RDEN_SERD2_MASK (0x4U) 445 #define CSTCU_RDEN_SERD2_SHIFT (2U) 446 #define CSTCU_RDEN_SERD2_WIDTH (1U) 447 #define CSTCU_RDEN_SERD2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDEN_SERD2_SHIFT)) & CSTCU_RDEN_SERD2_MASK) 448 449 #define CSTCU_RDEN_SERD3_MASK (0x8U) 450 #define CSTCU_RDEN_SERD3_SHIFT (3U) 451 #define CSTCU_RDEN_SERD3_WIDTH (1U) 452 #define CSTCU_RDEN_SERD3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDEN_SERD3_SHIFT)) & CSTCU_RDEN_SERD3_MASK) 453 /*! @} */ 454 455 /*! @name RDENSTAT - Reset Domain Enable Status */ 456 /*! @{ */ 457 458 #define CSTCU_RDENSTAT_SESRD0_MASK (0x1U) 459 #define CSTCU_RDENSTAT_SESRD0_SHIFT (0U) 460 #define CSTCU_RDENSTAT_SESRD0_WIDTH (1U) 461 #define CSTCU_RDENSTAT_SESRD0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDENSTAT_SESRD0_SHIFT)) & CSTCU_RDENSTAT_SESRD0_MASK) 462 463 #define CSTCU_RDENSTAT_SESRD1_MASK (0x2U) 464 #define CSTCU_RDENSTAT_SESRD1_SHIFT (1U) 465 #define CSTCU_RDENSTAT_SESRD1_WIDTH (1U) 466 #define CSTCU_RDENSTAT_SESRD1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDENSTAT_SESRD1_SHIFT)) & CSTCU_RDENSTAT_SESRD1_MASK) 467 468 #define CSTCU_RDENSTAT_SESRD2_MASK (0x4U) 469 #define CSTCU_RDENSTAT_SESRD2_SHIFT (2U) 470 #define CSTCU_RDENSTAT_SESRD2_WIDTH (1U) 471 #define CSTCU_RDENSTAT_SESRD2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDENSTAT_SESRD2_SHIFT)) & CSTCU_RDENSTAT_SESRD2_MASK) 472 473 #define CSTCU_RDENSTAT_SESRD3_MASK (0x8U) 474 #define CSTCU_RDENSTAT_SESRD3_SHIFT (3U) 475 #define CSTCU_RDENSTAT_SESRD3_WIDTH (1U) 476 #define CSTCU_RDENSTAT_SESRD3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_RDENSTAT_SESRD3_SHIFT)) & CSTCU_RDENSTAT_SESRD3_MASK) 477 /*! @} */ 478 479 /*! @name LASTRDEN - Last Run Reset Domain Enable */ 480 /*! @{ */ 481 482 #define CSTCU_LASTRDEN_LRSERD0_MASK (0x1U) 483 #define CSTCU_LASTRDEN_LRSERD0_SHIFT (0U) 484 #define CSTCU_LASTRDEN_LRSERD0_WIDTH (1U) 485 #define CSTCU_LASTRDEN_LRSERD0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LASTRDEN_LRSERD0_SHIFT)) & CSTCU_LASTRDEN_LRSERD0_MASK) 486 487 #define CSTCU_LASTRDEN_LRSERD1_MASK (0x2U) 488 #define CSTCU_LASTRDEN_LRSERD1_SHIFT (1U) 489 #define CSTCU_LASTRDEN_LRSERD1_WIDTH (1U) 490 #define CSTCU_LASTRDEN_LRSERD1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LASTRDEN_LRSERD1_SHIFT)) & CSTCU_LASTRDEN_LRSERD1_MASK) 491 492 #define CSTCU_LASTRDEN_LRSERD2_MASK (0x4U) 493 #define CSTCU_LASTRDEN_LRSERD2_SHIFT (2U) 494 #define CSTCU_LASTRDEN_LRSERD2_WIDTH (1U) 495 #define CSTCU_LASTRDEN_LRSERD2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LASTRDEN_LRSERD2_SHIFT)) & CSTCU_LASTRDEN_LRSERD2_MASK) 496 497 #define CSTCU_LASTRDEN_LRSERD3_MASK (0x8U) 498 #define CSTCU_LASTRDEN_LRSERD3_SHIFT (3U) 499 #define CSTCU_LASTRDEN_LRSERD3_WIDTH (1U) 500 #define CSTCU_LASTRDEN_LRSERD3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LASTRDEN_LRSERD3_SHIFT)) & CSTCU_LASTRDEN_LRSERD3_MASK) 501 /*! @} */ 502 503 /*! @name BYPLSTCU - Bypass LSTCU */ 504 /*! @{ */ 505 506 #define CSTCU_BYPLSTCU_BYP_L0_MASK (0x1U) 507 #define CSTCU_BYPLSTCU_BYP_L0_SHIFT (0U) 508 #define CSTCU_BYPLSTCU_BYP_L0_WIDTH (1U) 509 #define CSTCU_BYPLSTCU_BYP_L0(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L0_SHIFT)) & CSTCU_BYPLSTCU_BYP_L0_MASK) 510 511 #define CSTCU_BYPLSTCU_BYP_L1_MASK (0x2U) 512 #define CSTCU_BYPLSTCU_BYP_L1_SHIFT (1U) 513 #define CSTCU_BYPLSTCU_BYP_L1_WIDTH (1U) 514 #define CSTCU_BYPLSTCU_BYP_L1(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L1_SHIFT)) & CSTCU_BYPLSTCU_BYP_L1_MASK) 515 516 #define CSTCU_BYPLSTCU_BYP_L2_MASK (0x4U) 517 #define CSTCU_BYPLSTCU_BYP_L2_SHIFT (2U) 518 #define CSTCU_BYPLSTCU_BYP_L2_WIDTH (1U) 519 #define CSTCU_BYPLSTCU_BYP_L2(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L2_SHIFT)) & CSTCU_BYPLSTCU_BYP_L2_MASK) 520 521 #define CSTCU_BYPLSTCU_BYP_L3_MASK (0x8U) 522 #define CSTCU_BYPLSTCU_BYP_L3_SHIFT (3U) 523 #define CSTCU_BYPLSTCU_BYP_L3_WIDTH (1U) 524 #define CSTCU_BYPLSTCU_BYP_L3(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L3_SHIFT)) & CSTCU_BYPLSTCU_BYP_L3_MASK) 525 526 #define CSTCU_BYPLSTCU_BYP_L4_MASK (0x10U) 527 #define CSTCU_BYPLSTCU_BYP_L4_SHIFT (4U) 528 #define CSTCU_BYPLSTCU_BYP_L4_WIDTH (1U) 529 #define CSTCU_BYPLSTCU_BYP_L4(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L4_SHIFT)) & CSTCU_BYPLSTCU_BYP_L4_MASK) 530 531 #define CSTCU_BYPLSTCU_BYP_L5_MASK (0x20U) 532 #define CSTCU_BYPLSTCU_BYP_L5_SHIFT (5U) 533 #define CSTCU_BYPLSTCU_BYP_L5_WIDTH (1U) 534 #define CSTCU_BYPLSTCU_BYP_L5(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L5_SHIFT)) & CSTCU_BYPLSTCU_BYP_L5_MASK) 535 536 #define CSTCU_BYPLSTCU_BYP_L6_MASK (0x40U) 537 #define CSTCU_BYPLSTCU_BYP_L6_SHIFT (6U) 538 #define CSTCU_BYPLSTCU_BYP_L6_WIDTH (1U) 539 #define CSTCU_BYPLSTCU_BYP_L6(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L6_SHIFT)) & CSTCU_BYPLSTCU_BYP_L6_MASK) 540 541 #define CSTCU_BYPLSTCU_BYP_L7_MASK (0x80U) 542 #define CSTCU_BYPLSTCU_BYP_L7_SHIFT (7U) 543 #define CSTCU_BYPLSTCU_BYP_L7_WIDTH (1U) 544 #define CSTCU_BYPLSTCU_BYP_L7(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L7_SHIFT)) & CSTCU_BYPLSTCU_BYP_L7_MASK) 545 546 #define CSTCU_BYPLSTCU_BYP_L8_MASK (0x100U) 547 #define CSTCU_BYPLSTCU_BYP_L8_SHIFT (8U) 548 #define CSTCU_BYPLSTCU_BYP_L8_WIDTH (1U) 549 #define CSTCU_BYPLSTCU_BYP_L8(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L8_SHIFT)) & CSTCU_BYPLSTCU_BYP_L8_MASK) 550 551 #define CSTCU_BYPLSTCU_BYP_L9_MASK (0x200U) 552 #define CSTCU_BYPLSTCU_BYP_L9_SHIFT (9U) 553 #define CSTCU_BYPLSTCU_BYP_L9_WIDTH (1U) 554 #define CSTCU_BYPLSTCU_BYP_L9(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L9_SHIFT)) & CSTCU_BYPLSTCU_BYP_L9_MASK) 555 556 #define CSTCU_BYPLSTCU_BYP_L10_MASK (0x400U) 557 #define CSTCU_BYPLSTCU_BYP_L10_SHIFT (10U) 558 #define CSTCU_BYPLSTCU_BYP_L10_WIDTH (1U) 559 #define CSTCU_BYPLSTCU_BYP_L10(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L10_SHIFT)) & CSTCU_BYPLSTCU_BYP_L10_MASK) 560 561 #define CSTCU_BYPLSTCU_BYP_L11_MASK (0x800U) 562 #define CSTCU_BYPLSTCU_BYP_L11_SHIFT (11U) 563 #define CSTCU_BYPLSTCU_BYP_L11_WIDTH (1U) 564 #define CSTCU_BYPLSTCU_BYP_L11(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L11_SHIFT)) & CSTCU_BYPLSTCU_BYP_L11_MASK) 565 566 #define CSTCU_BYPLSTCU_BYP_L12_MASK (0x1000U) 567 #define CSTCU_BYPLSTCU_BYP_L12_SHIFT (12U) 568 #define CSTCU_BYPLSTCU_BYP_L12_WIDTH (1U) 569 #define CSTCU_BYPLSTCU_BYP_L12(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L12_SHIFT)) & CSTCU_BYPLSTCU_BYP_L12_MASK) 570 571 #define CSTCU_BYPLSTCU_BYP_L13_MASK (0x2000U) 572 #define CSTCU_BYPLSTCU_BYP_L13_SHIFT (13U) 573 #define CSTCU_BYPLSTCU_BYP_L13_WIDTH (1U) 574 #define CSTCU_BYPLSTCU_BYP_L13(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L13_SHIFT)) & CSTCU_BYPLSTCU_BYP_L13_MASK) 575 576 #define CSTCU_BYPLSTCU_BYP_L14_MASK (0x4000U) 577 #define CSTCU_BYPLSTCU_BYP_L14_SHIFT (14U) 578 #define CSTCU_BYPLSTCU_BYP_L14_WIDTH (1U) 579 #define CSTCU_BYPLSTCU_BYP_L14(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L14_SHIFT)) & CSTCU_BYPLSTCU_BYP_L14_MASK) 580 581 #define CSTCU_BYPLSTCU_BYP_L15_MASK (0x8000U) 582 #define CSTCU_BYPLSTCU_BYP_L15_SHIFT (15U) 583 #define CSTCU_BYPLSTCU_BYP_L15_WIDTH (1U) 584 #define CSTCU_BYPLSTCU_BYP_L15(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L15_SHIFT)) & CSTCU_BYPLSTCU_BYP_L15_MASK) 585 586 #define CSTCU_BYPLSTCU_BYP_L16_MASK (0x10000U) 587 #define CSTCU_BYPLSTCU_BYP_L16_SHIFT (16U) 588 #define CSTCU_BYPLSTCU_BYP_L16_WIDTH (1U) 589 #define CSTCU_BYPLSTCU_BYP_L16(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L16_SHIFT)) & CSTCU_BYPLSTCU_BYP_L16_MASK) 590 591 #define CSTCU_BYPLSTCU_BYP_L17_MASK (0x20000U) 592 #define CSTCU_BYPLSTCU_BYP_L17_SHIFT (17U) 593 #define CSTCU_BYPLSTCU_BYP_L17_WIDTH (1U) 594 #define CSTCU_BYPLSTCU_BYP_L17(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L17_SHIFT)) & CSTCU_BYPLSTCU_BYP_L17_MASK) 595 596 #define CSTCU_BYPLSTCU_BYP_L18_MASK (0x40000U) 597 #define CSTCU_BYPLSTCU_BYP_L18_SHIFT (18U) 598 #define CSTCU_BYPLSTCU_BYP_L18_WIDTH (1U) 599 #define CSTCU_BYPLSTCU_BYP_L18(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L18_SHIFT)) & CSTCU_BYPLSTCU_BYP_L18_MASK) 600 601 #define CSTCU_BYPLSTCU_BYP_L19_MASK (0x80000U) 602 #define CSTCU_BYPLSTCU_BYP_L19_SHIFT (19U) 603 #define CSTCU_BYPLSTCU_BYP_L19_WIDTH (1U) 604 #define CSTCU_BYPLSTCU_BYP_L19(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_BYPLSTCU_BYP_L19_SHIFT)) & CSTCU_BYPLSTCU_BYP_L19_MASK) 605 /*! @} */ 606 607 /*! @name STAG - Stagger */ 608 /*! @{ */ 609 610 #define CSTCU_STAG_MB_DELAY_MASK (0xFF00U) 611 #define CSTCU_STAG_MB_DELAY_SHIFT (8U) 612 #define CSTCU_STAG_MB_DELAY_WIDTH (8U) 613 #define CSTCU_STAG_MB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_STAG_MB_DELAY_SHIFT)) & CSTCU_STAG_MB_DELAY_MASK) 614 615 #define CSTCU_STAG_LB_DELAY_MASK (0xFF0000U) 616 #define CSTCU_STAG_LB_DELAY_SHIFT (16U) 617 #define CSTCU_STAG_LB_DELAY_WIDTH (8U) 618 #define CSTCU_STAG_LB_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_STAG_LB_DELAY_SHIFT)) & CSTCU_STAG_LB_DELAY_MASK) 619 /*! @} */ 620 621 /*! @name LMBPTR - LSTCU MBIST Run Phase Scheduler Pointer */ 622 /*! @{ */ 623 624 #define CSTCU_LMBPTR_MBPTR_MASK (0xFFU) 625 #define CSTCU_LMBPTR_MBPTR_SHIFT (0U) 626 #define CSTCU_LMBPTR_MBPTR_WIDTH (8U) 627 #define CSTCU_LMBPTR_MBPTR(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LMBPTR_MBPTR_SHIFT)) & CSTCU_LMBPTR_MBPTR_MASK) 628 629 #define CSTCU_LMBPTR_MBCSM_MASK (0x100U) 630 #define CSTCU_LMBPTR_MBCSM_SHIFT (8U) 631 #define CSTCU_LMBPTR_MBCSM_WIDTH (1U) 632 #define CSTCU_LMBPTR_MBCSM(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LMBPTR_MBCSM_SHIFT)) & CSTCU_LMBPTR_MBCSM_MASK) 633 634 #define CSTCU_LMBPTR_MBEOL_MASK (0x80000000U) 635 #define CSTCU_LMBPTR_MBEOL_SHIFT (31U) 636 #define CSTCU_LMBPTR_MBEOL_WIDTH (1U) 637 #define CSTCU_LMBPTR_MBEOL(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LMBPTR_MBEOL_SHIFT)) & CSTCU_LMBPTR_MBEOL_MASK) 638 /*! @} */ 639 640 /*! @name LLBPTR - LSTCU LBIST Run phase Scheduler Pointer */ 641 /*! @{ */ 642 643 #define CSTCU_LLBPTR_LBPTR_MASK (0xFFU) 644 #define CSTCU_LLBPTR_LBPTR_SHIFT (0U) 645 #define CSTCU_LLBPTR_LBPTR_WIDTH (8U) 646 #define CSTCU_LLBPTR_LBPTR(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LLBPTR_LBPTR_SHIFT)) & CSTCU_LLBPTR_LBPTR_MASK) 647 648 #define CSTCU_LLBPTR_LBCSM_MASK (0x100U) 649 #define CSTCU_LLBPTR_LBCSM_SHIFT (8U) 650 #define CSTCU_LLBPTR_LBCSM_WIDTH (1U) 651 #define CSTCU_LLBPTR_LBCSM(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LLBPTR_LBCSM_SHIFT)) & CSTCU_LLBPTR_LBCSM_MASK) 652 653 #define CSTCU_LLBPTR_LBEOL_MASK (0x80000000U) 654 #define CSTCU_LLBPTR_LBEOL_SHIFT (31U) 655 #define CSTCU_LLBPTR_LBEOL_WIDTH (1U) 656 #define CSTCU_LLBPTR_LBEOL(x) (((uint32_t)(((uint32_t)(x)) << CSTCU_LLBPTR_LBEOL_SHIFT)) & CSTCU_LLBPTR_LBEOL_MASK) 657 /*! @} */ 658 659 /*! 660 * @} 661 */ /* end of group CSTCU_Register_Masks */ 662 663 /*! 664 * @} 665 */ /* end of group CSTCU_Peripheral_Access_Layer */ 666 667 #endif /* #if !defined(S32Z2_CSTCU_H_) */ 668
