1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2024 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CRC.h 10 * @version 2.3 11 * @date 2024-05-03 12 * @brief Peripheral Access Layer for S32Z2_CRC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CRC_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CRC_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CRC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CRC - Size of Registers Arrays */ 72 #define CRC_CHANNEL_COUNT 3u 73 74 /** CRC - Register Layout Typedef */ 75 typedef struct { 76 struct CRC_CHANNEL { /* offset: 0x0, array step: 0x10 */ 77 __IO uint32_t CFG; /**< Configuration Register, array offset: 0x0, array step: 0x10 */ 78 __IO uint32_t INP; /**< Input Register, array offset: 0x4, array step: 0x10 */ 79 __IO uint32_t CSTAT; /**< Current Status Register, array offset: 0x8, array step: 0x10 */ 80 __I uint32_t OUTP; /**< Output Register, array offset: 0xC, array step: 0x10 */ 81 } CHANNEL[CRC_CHANNEL_COUNT]; 82 } CRC_Type, *CRC_MemMapPtr; 83 84 /** Number of instances of the CRC module. */ 85 #define CRC_INSTANCE_COUNT (8u) 86 87 /* CRC - Peripheral instance base addresses */ 88 /** Peripheral CE_CRC_0 base address */ 89 #define IP_CE_CRC_0_BASE (0x44A88000u) 90 /** Peripheral CE_CRC_0 base pointer */ 91 #define IP_CE_CRC_0 ((CRC_Type *)IP_CE_CRC_0_BASE) 92 /** Peripheral CE_CRC_1 base address */ 93 #define IP_CE_CRC_1_BASE (0x44A98000u) 94 /** Peripheral CE_CRC_1 base pointer */ 95 #define IP_CE_CRC_1 ((CRC_Type *)IP_CE_CRC_1_BASE) 96 /** Peripheral CE_CRC_2 base address */ 97 #define IP_CE_CRC_2_BASE (0x44AA8000u) 98 /** Peripheral CE_CRC_2 base pointer */ 99 #define IP_CE_CRC_2 ((CRC_Type *)IP_CE_CRC_2_BASE) 100 /** Peripheral CE_CRC_3 base address */ 101 #define IP_CE_CRC_3_BASE (0x44AB8000u) 102 /** Peripheral CE_CRC_3 base pointer */ 103 #define IP_CE_CRC_3 ((CRC_Type *)IP_CE_CRC_3_BASE) 104 /** Peripheral CE_CRC_4 base address */ 105 #define IP_CE_CRC_4_BASE (0x44AC8000u) 106 /** Peripheral CE_CRC_4 base pointer */ 107 #define IP_CE_CRC_4 ((CRC_Type *)IP_CE_CRC_4_BASE) 108 /** Peripheral CE_CRC_5 base address */ 109 #define IP_CE_CRC_5_BASE (0x44AD8000u) 110 /** Peripheral CE_CRC_5 base pointer */ 111 #define IP_CE_CRC_5 ((CRC_Type *)IP_CE_CRC_5_BASE) 112 /** Peripheral RTU0__CRC base address */ 113 #define IP_RTU0__CRC_BASE (0x761C0000u) 114 /** Peripheral RTU0__CRC base pointer */ 115 #define IP_RTU0__CRC ((CRC_Type *)IP_RTU0__CRC_BASE) 116 /** Peripheral RTU1__CRC base address */ 117 #define IP_RTU1__CRC_BASE (0x769C0000u) 118 /** Peripheral RTU1__CRC base pointer */ 119 #define IP_RTU1__CRC ((CRC_Type *)IP_RTU1__CRC_BASE) 120 /** Array initializer of CRC peripheral base addresses */ 121 #define IP_CRC_BASE_ADDRS { IP_CE_CRC_0_BASE, IP_CE_CRC_1_BASE, IP_CE_CRC_2_BASE, IP_CE_CRC_3_BASE, IP_CE_CRC_4_BASE, IP_CE_CRC_5_BASE, IP_RTU0__CRC_BASE, IP_RTU1__CRC_BASE } 122 /** Array initializer of CRC peripheral base pointers */ 123 #define IP_CRC_BASE_PTRS { IP_CE_CRC_0, IP_CE_CRC_1, IP_CE_CRC_2, IP_CE_CRC_3, IP_CE_CRC_4, IP_CE_CRC_5, IP_RTU0__CRC, IP_RTU1__CRC } 124 125 /* ---------------------------------------------------------------------------- 126 -- CRC Register Masks 127 ---------------------------------------------------------------------------- */ 128 129 /*! 130 * @addtogroup CRC_Register_Masks CRC Register Masks 131 * @{ 132 */ 133 134 /*! @name CFG - Configuration Register */ 135 /*! @{ */ 136 137 #define CRC_CFG_INV_MASK (0x1U) 138 #define CRC_CFG_INV_SHIFT (0U) 139 #define CRC_CFG_INV_WIDTH (1U) 140 #define CRC_CFG_INV(x) (((uint32_t)(((uint32_t)(x)) << CRC_CFG_INV_SHIFT)) & CRC_CFG_INV_MASK) 141 142 #define CRC_CFG_SWAP_MASK (0x2U) 143 #define CRC_CFG_SWAP_SHIFT (1U) 144 #define CRC_CFG_SWAP_WIDTH (1U) 145 #define CRC_CFG_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CRC_CFG_SWAP_SHIFT)) & CRC_CFG_SWAP_MASK) 146 147 #define CRC_CFG_POLYG_MASK (0xCU) 148 #define CRC_CFG_POLYG_SHIFT (2U) 149 #define CRC_CFG_POLYG_WIDTH (2U) 150 #define CRC_CFG_POLYG(x) (((uint32_t)(((uint32_t)(x)) << CRC_CFG_POLYG_SHIFT)) & CRC_CFG_POLYG_MASK) 151 152 #define CRC_CFG_SWAP_BITWISE_MASK (0x10U) 153 #define CRC_CFG_SWAP_BITWISE_SHIFT (4U) 154 #define CRC_CFG_SWAP_BITWISE_WIDTH (1U) 155 #define CRC_CFG_SWAP_BITWISE(x) (((uint32_t)(((uint32_t)(x)) << CRC_CFG_SWAP_BITWISE_SHIFT)) & CRC_CFG_SWAP_BITWISE_MASK) 156 157 #define CRC_CFG_SWAP_BYTEWISE_MASK (0x20U) 158 #define CRC_CFG_SWAP_BYTEWISE_SHIFT (5U) 159 #define CRC_CFG_SWAP_BYTEWISE_WIDTH (1U) 160 #define CRC_CFG_SWAP_BYTEWISE(x) (((uint32_t)(((uint32_t)(x)) << CRC_CFG_SWAP_BYTEWISE_SHIFT)) & CRC_CFG_SWAP_BYTEWISE_MASK) 161 /*! @} */ 162 163 /*! @name INP - Input Register */ 164 /*! @{ */ 165 166 #define CRC_INP_INP_MASK (0xFFFFFFFFU) 167 #define CRC_INP_INP_SHIFT (0U) 168 #define CRC_INP_INP_WIDTH (32U) 169 #define CRC_INP_INP(x) (((uint32_t)(((uint32_t)(x)) << CRC_INP_INP_SHIFT)) & CRC_INP_INP_MASK) 170 /*! @} */ 171 172 /*! @name CSTAT - Current Status Register */ 173 /*! @{ */ 174 175 #define CRC_CSTAT_CSTAT_MASK (0xFFFFFFFFU) 176 #define CRC_CSTAT_CSTAT_SHIFT (0U) 177 #define CRC_CSTAT_CSTAT_WIDTH (32U) 178 #define CRC_CSTAT_CSTAT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CSTAT_CSTAT_SHIFT)) & CRC_CSTAT_CSTAT_MASK) 179 /*! @} */ 180 181 /*! @name OUTP - Output Register */ 182 /*! @{ */ 183 184 #define CRC_OUTP_OUTP_MASK (0xFFFFFFFFU) 185 #define CRC_OUTP_OUTP_SHIFT (0U) 186 #define CRC_OUTP_OUTP_WIDTH (32U) 187 #define CRC_OUTP_OUTP(x) (((uint32_t)(((uint32_t)(x)) << CRC_OUTP_OUTP_SHIFT)) & CRC_OUTP_OUTP_MASK) 188 /*! @} */ 189 190 /*! 191 * @} 192 */ /* end of group CRC_Register_Masks */ 193 194 /*! 195 * @} 196 */ /* end of group CRC_Peripheral_Access_Layer */ 197 198 #endif /* #if !defined(S32Z2_CRC_H_) */ 199
