Home
last modified time | relevance | path

Searched refs:CR1 (Results 1 – 25 of 89) sorted by relevance

1234

/hal_nxp-latest/mcux/mcux-sdk/drivers/cmp/
Dfsl_cmp.c84 …tmp8 = (uint8_t)(base->CR1 & ~(CMP_CR1_PMODE_MASK | CMP_CR1_INV_MASK | CMP_CR1_COS_MASK | CMP_CR1_… in CMP_Init()
111 base->CR1 = tmp8; in CMP_Init()
138 base->CR1 = 0U; in CMP_Deinit()
243 base->CR1 |= CMP_CR1_SE_MASK; /* Choose the external SAMPLE clock. */ in CMP_SetFilterConfig()
247 base->CR1 &= (uint8_t)(~CMP_CR1_SE_MASK); /* Choose the internal divided bus clock. */ in CMP_SetFilterConfig()
Dfsl_cmp.h158 base->CR1 |= CMP_CR1_EN_MASK; in CMP_Enable()
162 base->CR1 &= ~(uint8_t)CMP_CR1_EN_MASK; in CMP_Enable()
229 base->CR1 |= CMP_CR1_WE_MASK; in CMP_EnableWindowMode()
233 base->CR1 &= (uint8_t)(~CMP_CR1_WE_MASK); in CMP_EnableWindowMode()
/hal_nxp-latest/mcux/mcux-sdk/drivers/erm/
Dfsl_erm.h107 temp = base->CR1; in ERM_EnableInterrupts()
108 base->CR1 = (temp & ~(0x0CUL << ((0x07U + 0x08U - (uint32_t)channel) * 4U))) | in ERM_EnableInterrupts()
131 base->CR1 &= ~(mask << ((0x07U + 0x08U - (uint32_t)channel) * 4U)); in ERM_DisableInterrupts()
Dfsl_erm.c69 base->CR1 = 0x00U; in ERM_Init()
/hal_nxp-latest/mcux/mcux-sdk/drivers/csi/
Dfsl_csi.h28 #define CSI_REG_CR1(base) (base)->CR1
/hal_nxp-latest/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_ERM_GTM.h74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ member
DS32Z2_ERM.h74 …__IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4, a… member
/hal_nxp-latest/s32/drivers/s32k3/BaseNXP/header/
DS32K344_ERM.h74 __IO uint32_t CR1; /**< ERM Configuration Register 1, offset: 0x4 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h598 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h763 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/
DMCXC141.h834 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/
DMCXC142.h832 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h604 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/
DMCXC242.h834 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h772 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h831 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h803 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/
DMCXC244.h805 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h835 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h749 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h848 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h740 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h711 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ member
730 #define CMP_CR1_REG(base) ((base)->CR1)

1234