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Searched refs:CMP_C1_INPSEL_MASK (Results 1 – 23 of 23) sorted by relevance

/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K144W_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K116_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K118_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K146_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K142_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K142W_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K148_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
DS32K144_CMP.h262 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
265 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/drivers/acmp/
Dfsl_acmp.c247 tmp32 &= ~CMP_C1_INPSEL_MASK; in ACMP_SetChannelConfig()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h989 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
997 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h990 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
998 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h988 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
996 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h1177 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1185 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h1174 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1182 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h1179 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1187 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h1178 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1186 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h1107 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1115 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h1176 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1184 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h1108 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1116 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h1175 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1183 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h1880 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
1888 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h2882 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
2890 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h2878 #define CMP_C1_INPSEL_MASK (0x18000000U) macro
2886 … (((uint32_t)(((uint32_t)(x)) << CMP_C1_INPSEL_SHIFT)) & CMP_C1_INPSEL_MASK)