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Searched refs:CMP_C0_CFR_MASK (Results 1 – 25 of 75) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/drivers/acmp/
Dfsl_acmp.c589 if (CMP_C0_CFR_MASK == (tmp32 & CMP_C0_CFR_MASK)) in ACMP_GetStatusFlags()
614 uint32_t tmp32 = (base->C0 & (~(CMP_C0_CFR_MASK | CMP_C0_CFF_MASK))); in ACMP_ClearStatusFlags()
619 tmp32 |= CMP_C0_CFR_MASK; in ACMP_ClearStatusFlags()
Dfsl_acmp.h30 #define CMP_C0_CFx_MASK (CMP_C0_CFR_MASK | CMP_C0_CFF_MASK)
50 …kACMP_OutputRisingEventFlag = CMP_C0_CFR_MASK, /*!< Rising-edge on compare output has occurred. …
/hal_nxp-latest/s32/drivers/s32k1/BaseNXP/header/
DS32K144W_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K116_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K118_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K146_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K142_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K142W_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K148_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
DS32K144_CMP.h168 #define CMP_C0_CFR_MASK (0x4000000U) macro
171 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z4/
DMKE14Z4.h863 #define CMP_C0_CFR_MASK (0x4000000U) macro
869 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z4/
DMKE15Z4.h864 #define CMP_C0_CFR_MASK (0x4000000U) macro
870 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16Z4/
DMKE16Z4.h862 #define CMP_C0_CFR_MASK (0x4000000U) macro
868 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z7/
DMKE12Z7.h1033 #define CMP_C0_CFR_MASK (0x4000000U) macro
1039 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE12Z9/
DMKE12Z9.h1039 #define CMP_C0_CFR_MASK (0x4000000U) macro
1045 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z7/
DMKE17Z7.h1035 #define CMP_C0_CFR_MASK (0x4000000U) macro
1041 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z7/
DMKE13Z7.h1034 #define CMP_C0_CFR_MASK (0x4000000U) macro
1040 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14Z7/
DMKE14Z7.h981 #define CMP_C0_CFR_MASK (0x4000000U) macro
987 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE17Z9/
DMKE17Z9.h1041 #define CMP_C0_CFR_MASK (0x4000000U) macro
1047 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE15Z7/
DMKE15Z7.h982 #define CMP_C0_CFR_MASK (0x4000000U) macro
988 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE13Z9/
DMKE13Z9.h1040 #define CMP_C0_CFR_MASK (0x4000000U) macro
1046 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h1736 #define CMP_C0_CFR_MASK (0x4000000U) macro
1742 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h2738 #define CMP_C0_CFR_MASK (0x4000000U) macro
2744 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h2734 #define CMP_C0_CFR_MASK (0x4000000U) macro
2740 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h4735 #define CMP_C0_CFR_MASK (0x4000000U) macro
4741 …x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)

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