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Searched refs:CMP2_BASE (Results 1 – 25 of 45) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MKE14F16/
DMKE14F16.h2002 #define CMP2_BASE (0x40075000u) macro
2004 #define CMP2 ((CMP_Type *)CMP2_BASE)
2006 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE18F16/
DMKE18F16.h3004 #define CMP2_BASE (0x40075000u) macro
3006 #define CMP2 ((CMP_Type *)CMP2_BASE)
3008 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE16F16/
DMKE16F16.h3000 #define CMP2_BASE (0x40075000u) macro
3002 #define CMP2 ((CMP_Type *)CMP2_BASE)
3004 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h4897 #define CMP2_BASE (0x40073010u) macro
4899 #define CMP2 ((CMP_Type *)CMP2_BASE)
4901 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM35Z7/
DMKM35Z7.h3721 #define CMP2_BASE (0x40072010u) macro
3723 #define CMP2 ((CMP_Type *)CMP2_BASE)
3725 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKM34Z7/
DMKM34Z7.h3790 #define CMP2_BASE (0x40072010u) macro
3792 #define CMP2 ((CMP_Type *)CMP2_BASE)
3796 CMP0_BASE, CMP1_BASE, CMP2_BASE \
/hal_nxp-latest/mcux/mcux-sdk/devices/MK24F12/
DMK24F12.h6734 #define CMP2_BASE (0x40073010u) macro
6736 #define CMP2 ((CMP_Type *)CMP2_BASE)
6738 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK63F12/
DMK63F12.h6763 #define CMP2_BASE (0x40073010u) macro
6765 #define CMP2 ((CMP_Type *)CMP2_BASE)
6767 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK64F12/
DMK64F12.h6776 #define CMP2_BASE (0x40073010u) macro
6778 #define CMP2 ((CMP_Type *)CMP2_BASE)
6780 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV56F24/
DMKV56F24.h7204 #define CMP2_BASE (0x40073010u) macro
7206 #define CMP2 ((CMP_Type *)CMP2_BASE)
7212 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV58F24/
DMKV58F24.h7208 #define CMP2_BASE (0x40073010u) macro
7210 #define CMP2 ((CMP_Type *)CMP2_BASE)
7216 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK66F18/
DMK66F18.h6834 #define CMP2_BASE (0x40073010u) macro
6836 #define CMP2 ((CMP_Type *)CMP2_BASE)
6842 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK26F18/
DMK26F18.h6783 #define CMP2_BASE (0x40073010u) macro
6785 #define CMP2 ((CMP_Type *)CMP2_BASE)
6791 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK65F18/
DMK65F18.h6834 #define CMP2_BASE (0x40073010u) macro
6836 #define CMP2 ((CMP_Type *)CMP2_BASE)
6842 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/
DMCXN946_cm33_core0.h47460 #define CMP2_BASE (0x50053000u) macro
47464 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47468 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
47485 #define CMP2_BASE (0x40053000u) macro
47487 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47489 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
DMCXN946_cm33_core1.h47460 #define CMP2_BASE (0x50053000u) macro
47464 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47468 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
47485 #define CMP2_BASE (0x40053000u) macro
47487 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47489 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN947/
DMCXN947_cm33_core1.h47460 #define CMP2_BASE (0x50053000u) macro
47464 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47468 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
47485 #define CMP2_BASE (0x40053000u) macro
47487 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47489 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
DMCXN947_cm33_core0.h47460 #define CMP2_BASE (0x50053000u) macro
47464 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47468 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
47485 #define CMP2_BASE (0x40053000u) macro
47487 #define CMP2 ((LPCMP_Type *)CMP2_BASE)
47489 #define LPCMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h9441 #define CMP2_BASE (0x40094008u) macro
9443 #define CMP2 ((CMP_Type *)CMP2_BASE)
9453 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h9421 #define CMP2_BASE (0x40094008u) macro
9423 #define CMP2 ((CMP_Type *)CMP2_BASE)
9433 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h11534 #define CMP2_BASE (0x40094008u) macro
11536 #define CMP2 ((CMP_Type *)CMP2_BASE)
11546 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h10463 #define CMP2_BASE (0x40094008u) macro
10465 #define CMP2 ((CMP_Type *)CMP2_BASE)
10475 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h11536 #define CMP2_BASE (0x40094008u) macro
11538 #define CMP2 ((CMP_Type *)CMP2_BASE)
11548 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h10466 #define CMP2_BASE (0x40094008u) macro
10468 #define CMP2 ((CMP_Type *)CMP2_BASE)
10478 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h11854 #define CMP2_BASE (0x40094008u) macro
11856 #define CMP2 ((CMP_Type *)CMP2_BASE)
11866 #define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }

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