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Searched refs:CMP0 (Results 1 – 25 of 113) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/boards/frdmkv31f/
Dboard.h51 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke15z/
Dboard.h63 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2b/
Dboard.h51 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmkv11z/
Dboard.h65 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke16z/
Dboard.h62 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z/
Dboard.h62 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmke17z512/
Dboard.h41 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxc041/
Dboard.h66 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk22f/
Dboard.h46 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmk32l2a4s/
Dboard.h40 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/boards/frdmmcxc444/
Dboard.h54 #define BOARD_CMP_BASEADDR CMP0
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW30Z4/
DMKW30Z4.h858 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
859 #define CMP0_BASE_PTR (CMP0)
863 #define CMP_BASE_PTRS { CMP0 }
879 #define CMP0_CR0 CMP_CR0_REG(CMP0)
880 #define CMP0_CR1 CMP_CR1_REG(CMP0)
881 #define CMP0_FPR CMP_FPR_REG(CMP0)
882 #define CMP0_SCR CMP_SCR_REG(CMP0)
883 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
884 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW20Z4/
DMKW20Z4.h858 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
859 #define CMP0_BASE_PTR (CMP0)
863 #define CMP_BASE_PTRS { CMP0 }
879 #define CMP0_CR0 CMP_CR0_REG(CMP0)
880 #define CMP0_CR1 CMP_CR1_REG(CMP0)
881 #define CMP0_FPR CMP_FPR_REG(CMP0)
882 #define CMP0_SCR CMP_SCR_REG(CMP0)
883 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
884 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW40Z4/
DMKW40Z4.h858 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
859 #define CMP0_BASE_PTR (CMP0)
863 #define CMP_BASE_PTRS { CMP0 }
879 #define CMP0_CR0 CMP_CR0_REG(CMP0)
880 #define CMP0_CR1 CMP_CR1_REG(CMP0)
881 #define CMP0_FPR CMP_FPR_REG(CMP0)
882 #define CMP0_SCR CMP_SCR_REG(CMP0)
883 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
884 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/
DMCXC041.h829 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
833 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h982 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
986 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/
DMCXC141.h1081 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1085 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/
DMCXC142.h1079 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1083 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h711 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
715 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/
DMCXC242.h1081 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1085 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h991 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
995 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/
DMCXC144.h1052 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1056 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/
DMCXC143.h1052 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1056 #define CMP_BASE_PTRS { CMP0 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h1043 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1051 #define CMP_BASE_PTRS { CMP0, CMP1 }
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/
DMCXC243.h1050 #define CMP0 ((CMP_Type *)CMP0_BASE) macro
1054 #define CMP_BASE_PTRS { CMP0 }

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