Home
last modified time | relevance | path

Searched refs:CLK_XTAL_OSC_CLK (Results 1 – 25 of 53) sorted by relevance

123

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
Dsystem_MIMXRT798S_ezhv.h43 #ifndef CLK_XTAL_OSC_CLK
44 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
49 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT798S_hifi4.h53 #ifndef CLK_XTAL_OSC_CLK
54 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
61 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT798S_cm33_core1.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is u… macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT798S_hifi1.h53 #ifndef CLK_XTAL_OSC_CLK
54 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
61 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT798S_cm33_core0.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
Dsystem_MIMXRT735S_ezhv.h52 #ifndef CLK_XTAL_OSC_CLK
53 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
58 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT735S_cm33_core1.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is u… macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT735S_hifi1.h53 #ifndef CLK_XTAL_OSC_CLK
54 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
61 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT735S_cm33_core0.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
Dsystem_MIMXRT758S_ezhv.h52 #ifndef CLK_XTAL_OSC_CLK
53 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
58 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT758S_hifi1.h53 #ifndef CLK_XTAL_OSC_CLK
54 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
61 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT758S_cm33_core1.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is u… macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
Dsystem_MIMXRT758S_cm33_core0.h57 #ifndef CLK_XTAL_OSC_CLK
58 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock, set to 0 when external CLKIN is … macro
63 #define CLK_OSC_CLK ((CLK_XTAL_OSC_CLK != 0U) ? CLK_XTAL_OSC_CLK : CLK_EXT_CLKIN)
/hal_nxp-latest/mcux/mcux-sdk/devices/RW610/
Dsystem_RW610.c139 if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_40000KHZ) && (steps >= 75UL) && (steps <= 96UL)) in getTcpuFvcoFreq()
145 else if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ) && (steps >= 78UL) && (steps <= 100UL)) in getTcpuFvcoFreq()
173 …return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT… in getSysOscFreq()
183 return CLK_XTAL_OSC_CLK / 40U; in getLpOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/RW612/
Dsystem_RW612.c139 if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_40000KHZ) && (steps >= 75UL) && (steps <= 96UL)) in getTcpuFvcoFreq()
145 else if ((CLK_XTAL_OSC_CLK == CLK_XTAL_OSC_CLK_38400KHZ) && (steps >= 78UL) && (steps <= 100UL)) in getTcpuFvcoFreq()
173 …return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT… in getSysOscFreq()
183 return CLK_XTAL_OSC_CLK / 40U; in getLpOscFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
Dsystem_MIMXRT595S_dsp.h58 #ifndef CLK_XTAL_OSC_CLK
59 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
73 …((CLKCTL0->SYSOSCBYPASS == 0u) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1u) ? CLK_EXT_CLKIN…
Dsystem_MIMXRT595S_cm33.h63 #ifndef CLK_XTAL_OSC_CLK
64 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
78 …((CLKCTL0->SYSOSCBYPASS == 0u) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1u) ? CLK_EXT_CLKIN…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
Dsystem_MIMXRT555S.h63 #ifndef CLK_XTAL_OSC_CLK
64 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
78 …((CLKCTL0->SYSOSCBYPASS == 0u) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1u) ? CLK_EXT_CLKIN…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
Dsystem_MIMXRT533S.h63 #ifndef CLK_XTAL_OSC_CLK
64 #define CLK_XTAL_OSC_CLK 24000000u /* Default XTAL OSC clock */ macro
78 …((CLKCTL0->SYSOSCBYPASS == 0u) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1u) ? CLK_EXT_CLKIN…
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD5/
Dsystem_MIMX8UD5_cm33.c73 freq = CLK_XTAL_OSC_CLK; in getPll0Freq()
94 freq = CLK_XTAL_OSC_CLK; in getPll1Freq()
168 CGCOUTClock = CLK_XTAL_OSC_CLK; in SystemCoreClockUpdate()
Dsystem_MIMX8UD5_cm33.h62 #ifndef CLK_XTAL_OSC_CLK
63 #define CLK_XTAL_OSC_CLK 24000000U /* Default XTAL OSC clock */ macro
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD7/
Dsystem_MIMX8UD7_cm33.c73 freq = CLK_XTAL_OSC_CLK; in getPll0Freq()
94 freq = CLK_XTAL_OSC_CLK; in getPll1Freq()
168 CGCOUTClock = CLK_XTAL_OSC_CLK; in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US5/
Dsystem_MIMX8US5_cm33.c73 freq = CLK_XTAL_OSC_CLK; in getPll0Freq()
94 freq = CLK_XTAL_OSC_CLK; in getPll1Freq()
168 CGCOUTClock = CLK_XTAL_OSC_CLK; in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8US3/
Dsystem_MIMX8US3_cm33.c73 freq = CLK_XTAL_OSC_CLK; in getPll0Freq()
94 freq = CLK_XTAL_OSC_CLK; in getPll1Freq()
168 CGCOUTClock = CLK_XTAL_OSC_CLK; in SystemCoreClockUpdate()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMX8UD3/
Dsystem_MIMX8UD3_cm33.c73 freq = CLK_XTAL_OSC_CLK; in getPll0Freq()
94 freq = CLK_XTAL_OSC_CLK; in getPll1Freq()
168 CGCOUTClock = CLK_XTAL_OSC_CLK; in SystemCoreClockUpdate()

123