Home
last modified time | relevance | path

Searched refs:CLK_GATE_ABSTRACT_REG_OFFSET (Results 1 – 25 of 113) sorted by relevance

12345

/hal_nxp-latest/mcux/mcux-sdk/devices/MKE02Z4/drivers/
Dfsl_clock.h211 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
366 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
377 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC041/drivers/
Dfsl_clock.h208 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
358 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
369 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z1284/drivers/
Dfsl_clock.h226 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
387 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
398 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE04Z4/drivers/
Dfsl_clock.h220 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
365 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
376 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKE06Z4/drivers/
Dfsl_clock.h226 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
387 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
398 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC142/drivers/
Dfsl_clock.h253 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
418 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
429 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL17Z644/drivers/
Dfsl_clock.h254 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
419 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
430 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC141/drivers/
Dfsl_clock.h253 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
418 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
429 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC444/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC443/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B31A/drivers/
Dfsl_clock.h272 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
440 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
451 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC144/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC244/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC242/drivers/
Dfsl_clock.h259 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
425 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
436 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC243/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKL27Z644/drivers/
Dfsl_clock.h260 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
426 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
437 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXC143/drivers/
Dfsl_clock.h271 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
439 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
450 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B11A/drivers/
Dfsl_clock.h272 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
440 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
451 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/K32L2B21A/drivers/
Dfsl_clock.h272 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
440 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
451 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKW41Z4/drivers/
Dfsl_clock.h326 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
582 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
593 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MK02F12810/drivers/
Dfsl_clock.h285 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
553 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
564 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV11Z7/drivers/
Dfsl_clock.h254 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
534 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV30F12810/drivers/
Dfsl_clock.h284 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
553 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
564 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z7/drivers/
Dfsl_clock.h257 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
519 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
530 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MKV10Z1287/drivers/
Dfsl_clock.h254 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIF… macro
523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_EnableClock()
534 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name); in CLOCK_DisableClock()

12345