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Searched refs:CLK_CTL4_PSCCTL0 (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h455 #define CLK_CTL4_PSCCTL0 10 /* CLKCTL_MED_VDD2 PSCCTL0 */ macro
680 kCLOCK_Axi0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 0), /*!< Clock gate name: AXI0*/
681 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 2), /*!< Clock gate name: VGPU*/
682 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 4), /*!< Clock gate name: MIPIDSI*/
683 kCLOCK_LPSpi16 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 5), /*!< Clock gate name: LPSPI16*/
684 kCLOCK_LPSpi14 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 6), /*!< Clock gate name: LPSPI14*/
685 kCLOCK_Xspi2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 8), /*!< Clock gate name: XSPI2*/
686 kCLOCK_Mmu2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 11), /*!< Clock gate name: MMU2*/
687 …kCLOCK_Glikey5 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON…
688 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 15), /*!< Clock gate name: FLEXIO0*/
[all …]
Dfsl_clock.c97 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
152 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
223 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()
251 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h455 #define CLK_CTL4_PSCCTL0 10 /* CLKCTL_MED_VDD2 PSCCTL0 */ macro
680 kCLOCK_Axi0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 0), /*!< Clock gate name: AXI0*/
681 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 2), /*!< Clock gate name: VGPU*/
682 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 4), /*!< Clock gate name: MIPIDSI*/
683 kCLOCK_LPSpi16 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 5), /*!< Clock gate name: LPSPI16*/
684 kCLOCK_LPSpi14 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 6), /*!< Clock gate name: LPSPI14*/
685 kCLOCK_Xspi2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 8), /*!< Clock gate name: XSPI2*/
686 kCLOCK_Mmu2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 11), /*!< Clock gate name: MMU2*/
687 …kCLOCK_Glikey5 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON…
688 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 15), /*!< Clock gate name: FLEXIO0*/
[all …]
Dfsl_clock.c97 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
152 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
223 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()
251 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h455 #define CLK_CTL4_PSCCTL0 10 /* CLKCTL_MED_VDD2 PSCCTL0 */ macro
680 kCLOCK_Axi0 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 0), /*!< Clock gate name: AXI0*/
681 kCLOCK_Gpu = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 2), /*!< Clock gate name: VGPU*/
682 kCLOCK_MipiDsiCtrl = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 4), /*!< Clock gate name: MIPIDSI*/
683 kCLOCK_LPSpi16 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 5), /*!< Clock gate name: LPSPI16*/
684 kCLOCK_LPSpi14 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 6), /*!< Clock gate name: LPSPI14*/
685 kCLOCK_Xspi2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 8), /*!< Clock gate name: XSPI2*/
686 kCLOCK_Mmu2 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 11), /*!< Clock gate name: MMU2*/
687 …kCLOCK_Glikey5 = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 13), /*!< Clock gate name: GLIKEY_SYSCON…
688 kCLOCK_Flexio = CLK_GATE_DEFINE(CLK_CTL4_PSCCTL0, 15), /*!< Clock gate name: FLEXIO0*/
[all …]
Dfsl_clock.c97 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
152 case CLK_CTL4_PSCCTL0: in CLOCK_EnableClock()
223 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()
251 case CLK_CTL4_PSCCTL0: in CLOCK_DisableClock()