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Searched refs:CLK_CTL3_PSCCTL0 (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/drivers/
Dfsl_clock.h454 #define CLK_CTL3_PSCCTL0 9 /* CLKCTL2 PSCCTL0 */ macro
662 kCLOCK_Cpu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 0), /*!< Clock gate name: CPU1*/
663 kCLOCK_Mu0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 4), /*!< Clock gate name: MU0*/
664 kCLOCK_Mu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 5), /*!< Clock gate name: MU1*/
665 kCLOCK_Mu2 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 6), /*!< Clock gate name: MU2*/
666 kCLOCK_OsTimer = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 7), /*!< Clock gate name: OsTimer*/
667 kCLOCK_Sema420 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 8), /*!< Clock gate name: SEMA42_0*/
668 kCLOCK_Sdadc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 9), /*!< Clock gate name: SDADC0*/
669 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 10), /*!< Clock gate name: SARADC0*/
670 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 11), /*!< Clock gate name: Acmp0*/
[all …]
Dfsl_clock.c91 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
146 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
220 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()
248 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/drivers/
Dfsl_clock.h454 #define CLK_CTL3_PSCCTL0 9 /* CLKCTL2 PSCCTL0 */ macro
662 kCLOCK_Cpu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 0), /*!< Clock gate name: CPU1*/
663 kCLOCK_Mu0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 4), /*!< Clock gate name: MU0*/
664 kCLOCK_Mu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 5), /*!< Clock gate name: MU1*/
665 kCLOCK_Mu2 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 6), /*!< Clock gate name: MU2*/
666 kCLOCK_OsTimer = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 7), /*!< Clock gate name: OsTimer*/
667 kCLOCK_Sema420 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 8), /*!< Clock gate name: SEMA42_0*/
668 kCLOCK_Sdadc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 9), /*!< Clock gate name: SDADC0*/
669 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 10), /*!< Clock gate name: SARADC0*/
670 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 11), /*!< Clock gate name: Acmp0*/
[all …]
Dfsl_clock.c91 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
146 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
220 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()
248 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/drivers/
Dfsl_clock.h454 #define CLK_CTL3_PSCCTL0 9 /* CLKCTL2 PSCCTL0 */ macro
662 kCLOCK_Cpu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 0), /*!< Clock gate name: CPU1*/
663 kCLOCK_Mu0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 4), /*!< Clock gate name: MU0*/
664 kCLOCK_Mu1 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 5), /*!< Clock gate name: MU1*/
665 kCLOCK_Mu2 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 6), /*!< Clock gate name: MU2*/
666 kCLOCK_OsTimer = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 7), /*!< Clock gate name: OsTimer*/
667 kCLOCK_Sema420 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 8), /*!< Clock gate name: SEMA42_0*/
668 kCLOCK_Sdadc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 9), /*!< Clock gate name: SDADC0*/
669 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 10), /*!< Clock gate name: SARADC0*/
670 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL3_PSCCTL0, 11), /*!< Clock gate name: Acmp0*/
[all …]
Dfsl_clock.c91 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
146 case CLK_CTL3_PSCCTL0: in CLOCK_EnableClock()
220 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()
248 case CLK_CTL3_PSCCTL0: in CLOCK_DisableClock()