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Searched refs:CLKCTL1_WDT1FCLKSEL_SEL_MASK (Results 1 – 12 of 12) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_clock.c820 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0)) in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_clock.c820 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0)) in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_clock.c838 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0)) in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_clock.c838 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0)) in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_clock.c838 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0)) in CLOCK_GetWdtClkFreq()
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h4495 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
4507 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
DMIMXRT685S_cm33.h10225 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
10237 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h10225 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
10237 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h6126 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
6138 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
DMIMXRT595S_cm33.h12383 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
12395 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h12379 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
12391 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h12382 #define CLKCTL1_WDT1FCLKSEL_SEL_MASK (0x7U) macro
12394 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_WDT1FCLKSEL_SEL_SHIFT)) & CLKCTL1_WDT1FCLKSEL_SEL_MASK)