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Searched refs:CLKCTL1_PSCCTL1_SET_CDOG3_MASK (Results 1 – 9 of 9) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/
DMIMXRT735S_hifi1.h11130 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11136 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT735S_cm33_core1.h11166 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11172 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT735S_ezhv.h20700 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
20706 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/
DMIMXRT758S_cm33_core1.h11166 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11172 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT758S_hifi1.h11130 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11136 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT758S_ezhv.h20700 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
20706 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/
DMIMXRT798S_hifi1.h11130 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11136 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT798S_cm33_core1.h11166 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
11172 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)
DMIMXRT798S_ezhv.h20700 #define CLKCTL1_PSCCTL1_SET_CDOG3_MASK (0x400000U) macro
20706 …(((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL1_SET_CDOG3_SHIFT)) & CLKCTL1_PSCCTL1_SET_CDOG3_MASK)