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Searched refs:CLKCTL1_PSCCTL0_FC1_CLK_MASK (Results 1 – 7 of 7) sorted by relevance

/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h2804 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
2810 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
DMIMXRT685S_cm33.h8534 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
8540 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h8534 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
8540 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h4192 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
4198 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
DMIMXRT595S_cm33.h10449 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
10455 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT533S/
DMIMXRT533S.h10445 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
10451 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)
/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT555S/
DMIMXRT555S.h10448 #define CLKCTL1_PSCCTL0_FC1_CLK_MASK (0x200U) macro
10454 … (((uint32_t)(((uint32_t)(x)) << CLKCTL1_PSCCTL0_FC1_CLK_SHIFT)) & CLKCTL1_PSCCTL0_FC1_CLK_MASK)